RTL Design Collection
A comprehensive repository of high-performance, synthesizable Register Transfer Level (RTL) designs. This project serves as a practical guide and library for digital logic implementation, targeting both FPGA and ASIC workflows.
This repository focuses on the bridge between high-level logic and physical hardware. It contains a curated selection of modules ranging from fundamental gates to complex state machines, all optimized for timing, area, and power.
- Synthesizable Code: Fully compatible with industry-standard tools like Vivado, Quartus, and Design Compiler.
- Modular Design: Optimized for reusability across different digital systems.
- Best Practices: Implements standard coding guidelines for clocking, resets, and signal synchronization.
The code is organized by complexity and function:
| Category | Description |
|---|---|
| Combinational | Muxes, Decoders, ALUs, and Priority Encoders. |
| Sequential | Flip-flops, Shift Registers, and Synchronous Counters. |
| FSMs | Moore and Mealy machines for control logic. |
| Memory | RAM/ROM models and FIFO implementations. |
- Clone the repo:
git clone [https://github.com/mannraval1/RTL.git](https://github.com/mannraval1/RTL.git)