Tm/jtag #32
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Tm/jtag #32
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This patch add basic routines for ADIv5. Possibly more of routines will be needed in future. Functions has to be added to ADIV5_AP_OPS_t.
This patch add memory routines to adiv5.c. This functions allow to read and write target's memory.
This patch add CortexM routines that will be needed to upload program to RAM of target device.
TMS and TDI should be set before rise of TCK. TDO should be read before fall of TCK. Add TMS parameter when passing TDI and reading TDO, because it can be done during transition from Shift-IR/DR to Exit1-IR/DR.
This patch expose CortexM specific operations for higher level driver.
This patch add routines that allow to program STM32F4xxx.
This patch add target.c which in future will contain functions that allow to register different targets. Target will have opaerations and private data that will be passed to all of its function. This allow to add abstraction over programmed targets. This patch also fix places where structure should be free in case of probing failure.
Add "STM32F4_" prefix to all defines in stm32f4.h, because some of them are defined in Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f429xx.h.
Sizeof return size in bytes, fixed assert in jtag_tdin. Don't skip devices without IDCODE. They still need to by bypassed. jtag_tdi return int now.
This patch add jtag_test function that allow to check by analizing output if connection is correct (you could shift DR in the loop and see IDCODEs and leater bits that where shifted in) TDO is changed to input insted of output (it is our input, TDO is output for debuged device). Low level JTAG logic is changed. Now it holds TCK up until next jtag_tdi request is issued. TCK is set to low in the same moment when TDI and TMS are setup. TDI is read right after rising edge of TCK.
Loop for next device while reading IR length will start with two bits readed instead of one.
This patch fix issues in low level JTAG driver that doesn't allow to identify STM32F4xx.
This patch fix flashing routine in four places: - Fix loop that detect EOF. - While erasing flash EOP is checked in FLASH_SR. EOP is only set if first in FLASH_CR value is set in register. - cortex pointer is saved in STM32F4_PRIV on successful detection. - Buffer for data that will be writen to target is now allocated on heap, no on stack, because leater one is more limited. Additionaly dealy on JTAG TCK is changed to allow faster transmision (currently it is aproximetly 15kHz).
Now target could be reset. Reset is also called after programing target.
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In this patchset connection to STM32F4xx via JTAG is added.