Implementation using PLAs
A Programmable Logic Array(PLA) is a structured-logic element composed of a set of inputs and their complements followed by two stages of logic.
- The first stage uses AND gates to generate product terms.
- The second stage uses OR gates to generate sum terms.
Sum of products are one of the two ways to form a canonical expression. Given that every logic function can be implemented using a canonical expression, PLAs can provide an implementation to virtually any design.
Consider the following 1-bit full adder:
The truth table for the same is as shown below:
| Inputs | Outputs | |||
|---|---|---|---|---|
| A | B | carryin | carryout | Sum |
| 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 0 | 1 |
| 0 | 1 | 0 | 0 | 1 |
| 0 | 1 | 1 | 1 | 0 |
| 1 | 0 | 0 | 0 | 1 |
| 1 | 0 | 1 | 1 | 0 |
| 1 | 1 | 0 | 1 | 0 |
| 1 | 1 | 1 | 1 | 1 |
We know that we can derive a canonical expression in the form of sum of products from the above truth table.
This circuit can be easily implemented as shown below:
A PLA drawn using dots to indicate the components of the product terms and sum terms in the array is shown below:
