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ARM Registers

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Rakshitha R edited this page Jul 19, 2024 · 1 revision

ARM Register Set

The ARM architecture is widely used in embedded systems and mobile devices, features a comprehensive set of registers crucial for its operation. image

General-Purpose Registers:

ARM processors typically have 16 general-purpose registers (R0 to R15):

  1. R0 to R12: Used for calculations and data storage during execution.
  2. R13 (SP): Stack Pointer, points to the top of the current stack for temporary data and return addresses.
  3. R14 (LR): Link Register, stores the return address for subroutine calls.
  4. R15 (PC): Program Counter, holds the address of the next instruction to execute.

Special-Purpose Registers:

1. CPSR (Current Program Status Register): Contains the current processor state, including condition flags (negative, zero, carry, overflow), interrupt disable bits, and mode information (user, system, supervisor, etc.). Condition Flags in CPSR The CPSR includes:

  • N (Negative): Set if the operation result is negative.
  • Z (Zero): Set if the operation result is zero.
  • C (Carry): Set if the operation results in a carry out.
  • V (Overflow): Set if the operation results in an overflow.

2. SPSR (Saved Program Status Register): Stores the CPSR value when exceptions occur, enabling the processor to return to the original state post-exception.

Banked Registers:

In certain modes (like FIQ), ARM has additional banked registers (e.g., R8_fiq to R12_fiq) for fast context switching without saving/restoring registers. This register set allows ARM processors to efficiently manage computational tasks, memory, and handle exceptions and interrupts effectively.

Mode-Specific Registers:

ARM processors operate in several modes, each tailored for specific tasks, with unique registers and behaviour to handle operations, exceptions, and interrupts efficiently. **1. User Mode: **

  • Purpose: Runs user applications.
  • Registers: General-purpose registers (R0-R12), SP (R13), LR (R14), PC (R15), and CPSR.
  • Access: No direct access to privileged operations.

2. FIQ (Fast Interrupt Request) Mode:

  • Purpose: Handles fast, high-priority interrupts.
  • Registers: R0-R7, banked registers (R8_fiq to R12_fiq), SP_fiq (R13), and LR_fiq (R14) for quicker interrupt handling.

3. IRQ (Interrupt Request) Mode:

  • Purpose: Manages standard interrupts.
  • Registers: R0-R12, Banked SP_irq (R13) and LR_irq (R14) to separate from User mode registers.

4. Supervisor (SVC) Mode:

  • Purpose: Performs operating system functions and high-privilege tasks.
  • Registers: R0-R12, Banked SP_svc (R13) and LR_svc (R14).
  • Entry: Triggered by a software interrupt instruction (SWI).

5. Undefined (UND) Mode:

  • Purpose: Handles undefined instructions.
  • Registers: R0-R12, Banked SP_und (R13) and LR_und (R14).

6. Abort Mode:

  • Purpose: Manages memory access violations.
  • Registers: R0-R12, Banked SP_abt (R13) and LR_abt (R14).

ARM Instruction Set and Register Use:

ARM processors use a load-store architecture that implies the operations are performed on registers and not directly on memory. Instructions include:

  • Data Processing Instructions: Perform arithmetic and logical operations on registers.
  • Load/Store Instructions: Transfer data between registers and memory.
  • Branch Instructions: Change the flow of execution by modifying the PC.
  • Status Register Access Instructions: Read and modify the CPSR and SPSR.

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