This repository contains three FPGA/Computer Architecture tutorials created under the advisement of Dr. Michelle McColgan and Professor Pauline White of Siena College to provide hands-on experience programming and interfacing with hardware in lab assignments for the CSIS220 Assembly Language and Computer Architecture course which Professor White is teaching. Siena College's Computer Science department has not used FPGAs before, so this gives students exposure and experience with the platform while solidifying knowledge of fundamental computer architecture concepts. All of these labs use the Digilent Basys3 FPGA development board and the Xilinx Vivado Design Suite version 2019.1.
The first tutorial shows how to build a half, full, and multi-bit adder circuit using logic gates in the Vivado IP Integrator.
The second tutorial demonstrates the universal gate theory, using RTL module instantiation to implement verilog coded NAND and NOR gates in the IP Integrator.
The third tutorial uses a verilog clock divider module originally from fpga4student and walks through some verilog basics, creating a top module which blinks LEDs at different speeds depending on which button of the Basys3 is pressed.
Verilog Operator list: https://personal.utdallas.edu/~jxw143630/index_files/Page5212.htm
Digilent FPGA tutorial page: https://reference.digilentinc.com/learn/programmable-logic/tutorials/start
Abacus Demo: https://reference.digilentinc.com/learn/programmable-logic/tutorials/basys-3-abacus/start