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A compact, hardware-oriented implementation of convolutional neural networks (CNNs) and supporting tools for simulation and FPGA/HDL integration.
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└─ Project
├─ build.sbt
├─ build.sc
├─ LICENSE
├─ /docs/
│ ├─ CNN.md
│ └─ LeNet5_README.md
├─ /src/
│ ├─ /main/
│ │ └─ /scala/
│ │ ├─ /cnn/
│ │ │ ├─ LeNet5.scala
│ │ │ └─ /Component/
│ │ │ ├─ Convolution.scala
│ │ │ ├─ FullConnection.scala
│ │ │ ├─ Matrix.scala
│ │ │ ├─ MaxPool.scala
│ │ │ ├─ ReLU.scala
│ │ │ └─ SystolicArray.scala
│ │ ├─ /misc/
│ │ │ ├─ Max.scala
│ │ │ ├─ MemTools.scala
│ │ │ └─ StreamMap.scala
│ │ └─ /soc/
│ └─ /test/
└─ /test/
├─ /project/
│ └─ /tang_primer/
└─ /software/
└─ /cybewithcnn/
├─ linker.ld
├─ Makefile
├─ /libs/
└─ /src/
OpenAccelerator is a research / tooling repository that contains Scala sources, HDL testbenches, weights and dataset examples for building and evaluating CNNs on hardware (FPGA/ASIC) and software simulators. The project mixes Scala (SBT) code, Verilog RTL, scripts and example data to exercise convolution, pooling and fully-connected layers.
This repository is aimed at developers and researchers who want to:
- prototype CNN dataflow in Scala and generate or integrate with Verilog modules
- simulate CNNs end-to-end using included testbenches and example vectors
- evaluate resource/weight layouts for hardware accelerators
- Scala-based project structure (SBT) with example modules under
src/main/scala - Verilog testbenches and binary memory images under
rtl/andLeNet5TestBench.* - Example dataset and weights in
test/LeNet5/to reproduce experiments - Documentation and notebooks in
docs/andtest/LeNet5/
Prerequisites
- Java (OpenJDK 8/11/17 recommended)
- sbt (Scala Build Tool)
- Verilog simulator (optional) such as ModelSim/iverilog for running HDL testbenches
Build the Scala project
-
From the repository root run:
sbt compile
Run tests (Scala)
sbt test
Run/inspect Verilog testbench (optional)
-
The
rtl/LeNet5TestBench.vand accompanying binary memory images inrtl/can be run in your HDL simulator. Files include:LeNet5TestBench.v— top-level Verilog testbenchLeNet5TestBench.v_toplevel_inputMem.bin— input image memoryLeNet5TestBench.v_toplevel_convWMem.bin— convolution weightsLeNet5TestBench.v_toplevel_fcWMem.bin— fully-connected weights
Refer to docs/ for more detailed instructions and examples.
Top-level important folders:
src/main/scala/— Scala sources (cnn, misc, soc)rtl/— Verilog testbench and memory imagesdocs/— documentation and imagestest/LeNet5/— notebooks and datasets for verificationproject/andtarget/— SBT project files and build artifacts
Contributions are what make the open source community such an amazing place to learn, inspire, and create. Any contributions you make are greatly appreciated.
If you have a suggestion that would make this better, please fork the repo and create a pull request. You can also simply open an issue with the tag "enhancement". Don't forget to give the project a star! Thanks again!
- Fork the Project
- Create your Feature Branch (
git checkout -b feature/AmazingFeature) - Commit your Changes (
git commit -m 'Add some AmazingFeature') - Push to the Branch (
git push origin feature/AmazingFeature) - Open a Pull Request
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Distributed under the MIT License. See LICENSE for more information.
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MoonGrt - 1561145394@qq.com Project Link: MoonGrt/OpenAccelerator
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