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OpenAccelerator

A compact, hardware-oriented implementation of convolutional neural networks (CNNs) and supporting tools for simulation and FPGA/HDL integration.
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Contents
  1. File Tree
  2. About The Project
  3. Contributing
  4. License
  5. Contact
  6. Acknowledgments

File Tree

└─ Project
  ├─ build.sbt
  ├─ build.sc
  ├─ LICENSE
  ├─ /docs/
  │ ├─ CNN.md
  │ └─ LeNet5_README.md
  ├─ /src/
  │ ├─ /main/
  │ │ └─ /scala/
  │ │   ├─ /cnn/
  │ │   │ ├─ LeNet5.scala
  │ │   │ └─ /Component/
  │ │   │   ├─ Convolution.scala
  │ │   │   ├─ FullConnection.scala
  │ │   │   ├─ Matrix.scala
  │ │   │   ├─ MaxPool.scala
  │ │   │   ├─ ReLU.scala
  │ │   │   └─ SystolicArray.scala
  │ │   ├─ /misc/
  │ │   │ ├─ Max.scala
  │ │   │ ├─ MemTools.scala
  │ │   │ └─ StreamMap.scala
  │ │   └─ /soc/
  │ └─ /test/
  └─ /test/
    ├─ /project/
    │ └─ /tang_primer/
    └─ /software/
      └─ /cybewithcnn/
        ├─ linker.ld
        ├─ Makefile
        ├─ /libs/
        └─ /src/

About The Project

Overview

OpenAccelerator is a research / tooling repository that contains Scala sources, HDL testbenches, weights and dataset examples for building and evaluating CNNs on hardware (FPGA/ASIC) and software simulators. The project mixes Scala (SBT) code, Verilog RTL, scripts and example data to exercise convolution, pooling and fully-connected layers.

This repository is aimed at developers and researchers who want to:

  • prototype CNN dataflow in Scala and generate or integrate with Verilog modules
  • simulate CNNs end-to-end using included testbenches and example vectors
  • evaluate resource/weight layouts for hardware accelerators

Key features

  • Scala-based project structure (SBT) with example modules under src/main/scala
  • Verilog testbenches and binary memory images under rtl/ and LeNet5TestBench.*
  • Example dataset and weights in test/LeNet5/ to reproduce experiments
  • Documentation and notebooks in docs/ and test/LeNet5/

Quick start

Prerequisites

  • Java (OpenJDK 8/11/17 recommended)
  • sbt (Scala Build Tool)
  • Verilog simulator (optional) such as ModelSim/iverilog for running HDL testbenches

Build the Scala project

  1. From the repository root run:

    sbt compile

Run tests (Scala)

sbt test

Run/inspect Verilog testbench (optional)

  • The rtl/LeNet5TestBench.v and accompanying binary memory images in rtl/ can be run in your HDL simulator. Files include:

    • LeNet5TestBench.v — top-level Verilog testbench
    • LeNet5TestBench.v_toplevel_inputMem.bin — input image memory
    • LeNet5TestBench.v_toplevel_convWMem.bin — convolution weights
    • LeNet5TestBench.v_toplevel_fcWMem.bin — fully-connected weights

Refer to docs/ for more detailed instructions and examples.

Repository layout

Top-level important folders:

  • src/main/scala/ — Scala sources (cnn, misc, soc)
  • rtl/ — Verilog testbench and memory images
  • docs/ — documentation and images
  • test/LeNet5/ — notebooks and datasets for verification
  • project/ and target/ — SBT project files and build artifacts

Contributing

Contributions are what make the open source community such an amazing place to learn, inspire, and create. Any contributions you make are greatly appreciated.

If you have a suggestion that would make this better, please fork the repo and create a pull request. You can also simply open an issue with the tag "enhancement". Don't forget to give the project a star! Thanks again!

  1. Fork the Project
  2. Create your Feature Branch (git checkout -b feature/AmazingFeature)
  3. Commit your Changes (git commit -m 'Add some AmazingFeature')
  4. Push to the Branch (git push origin feature/AmazingFeature)
  5. Open a Pull Request

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License

Distributed under the MIT License. See LICENSE for more information.

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Contact

MoonGrt - 1561145394@qq.com Project Link: MoonGrt/OpenAccelerator

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Acknowledgments

Use this space to list resources you find helpful and would like to give credit to. I've included a few of my favorites to kick things off!

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About

CNN on FPGA written in SpinalHDL, with components: Convolution, MaxPool, ReLU, FullConnection...

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Languages

  • Verilog 60.7%
  • C 29.0%
  • SystemVerilog 5.2%
  • Scala 2.1%
  • Rocq Prover 1.9%
  • Jupyter Notebook 0.8%
  • Other 0.3%