ChiselV - A RISC-V Processor in Chisel

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This project is a learning exercise for both writing a RISC-V core and also better understand Chisel, an HDL language based on Scala.

Currently the target is to have a RV32I core.

Planned features

• Add a standard bus like Wishbone
• Integrate peripherals thru this bus (UART, etc)
• Add memory controller for SDRAM or DDR