lake

Yet another RISC-V core implemented in Verilog

$ ./cc.sh # compile prog.c
$ mkdir build && cd build
$ cmake .. # configure project
$ make # build project
$ ./lake_test # run simulation

Name		Name	Last commit message	Last commit date
Latest commit History 5 Commits
.devcontainer		.devcontainer
.vscode		.vscode
tests		tests
.gitignore		.gitignore
CMakeLists.txt		CMakeLists.txt
README.md		README.md
adder.v		adder.v
alu.v		alu.v
cc.sh		cc.sh
ctrl.v		ctrl.v
dec.v		dec.v
dmem.v		dmem.v
entry.s		entry.s
imem.v		imem.v
immgen.v		immgen.v
lake.v		lake.v
link.ld		link.ld
mux2.v		mux2.v
mux4.v		mux4.v
pc.v		pc.v
prog.c		prog.c
regfile.v		regfile.v

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