Name		Name	Last commit message	Last commit date
Latest commit History 7 Commits
demo_srcs		demo_srcs
ip		ip
LICENSE		LICENSE
README.md		README.md

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security_stack

Set of security modules interfaced on the AXI4 bus

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Set of security modules interfaced on the AXI4 bus

GPL-3.0 license

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Verilog 48.3%
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C 8.2%
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