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APX support - added REX2 parsing.#374

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BissetJ merged 1 commit into
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users/ashedel/apx
May 21, 2026
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APX support - added REX2 parsing.#374
BissetJ merged 1 commit into
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users/ashedel/apx

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@ashedel ashedel commented May 20, 2026

This change adds Intel APX support to the Detours - REX2 prefix parsing and EVEX extensions handling.

@BissetJ BissetJ merged commit 9fdda4b into main May 21, 2026
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RatinCN added a commit to KNSoft/KNSoft.SlimDetours that referenced this pull request May 24, 2026
Handle Group 3 opcode extension /1 for F6/F7 the same as /0 when
sizing TEST immediates. Current CPUs execute these encodings as TEST
aliases, although public manuals only document /0.
RatinCN added a commit to KNSoft/KNSoft.SlimDetours that referenced this pull request May 24, 2026
Route opcode C7 through a dedicated copier so the documented XBEGIN encoding C7 F8 is relocated as a relative target while other C7 encodings continue to use the existing ModR/M plus imm16/32 sizing.
RatinCN added a commit to KNSoft/KNSoft.SlimDetours that referenced this pull request May 24, 2026
Recognize 0xD5 as the APX REX2 prefix on x64, dispatch the
prefixed opcode through MAP0/MAP1 according to the REX2 M bit,
and propagate REX2.W through the existing REX.W size handling.

Handle APX JMPABS target discovery for REX2 MAP0 A1 target64.
Per Intel APX, JMPABS only requires M=0 and W=0; other REX2
payload bits are ignored.
RatinCN added a commit to KNSoft/KNSoft.SlimDetours that referenced this pull request May 24, 2026
Route EVEX MAP5 through the MAP1/0F opcode table, matching the FP16 EVEX map layout instead of treating it like MAP2/0F38.

Add EVEX MAP4 dispatch through the legacy MAP0 opcode table for APX-promoted instructions, and stop treating EVEX P0 bit 3 as invalid because it is an APX register-extension bit rather than part of the map field.
RatinCN added a commit to KNSoft/KNSoft.SlimDetours that referenced this pull request May 25, 2026
…h fixes)

Sync the microsoft#374 behavior that sizes F6/F7 Group 3 opcode
extension /1 the same as /0 for TEST immediates.

Fix the upstream wording while porting: public Intel/AMD manuals do not
list /1 as a documented TEST form in the checked revisions, so keep the
code behavior but avoid claiming that /1 is publicly documented.
RatinCN added a commit to KNSoft/KNSoft.SlimDetours that referenced this pull request May 25, 2026
…h fixes)

Sync the microsoft#374 C7 copier so XBEGIN is relocated as a relative
target instead of being copied like MOV r/m, imm16/32.

Fix the upstream match while porting: XBEGIN is the exact C7 F8 rel16/32
encoding, so do not treat every C7 /7 ModR/M form as XBEGIN.
RatinCN added a commit to KNSoft/KNSoft.SlimDetours that referenced this pull request May 25, 2026
…xes)

Sync microsoft#374 support for recognizing 0xD5 as the APX REX2 prefix
on x64, dispatching MAP0/MAP1 according to REX2.M, and propagating
REX2.W through the existing REX.W size handling.

Fix the upstream JMPABS target check while porting: Intel APX only
requires REX2.M=0, REX2.W=0, and opcode A1 for JMPABS; other REX2
payload bits are ignored and must not prevent target discovery.
RatinCN added a commit to KNSoft/KNSoft.SlimDetours that referenced this pull request May 25, 2026
…with fixes)

Sync microsoft#374 EVEX map dispatch changes by routing MAP5 through the
MAP1/0F opcode table and MAP4 through the legacy MAP0 table for
APX-promoted instructions. Also stop rejecting EVEX P0 bit 3, which is
an APX register-extension bit rather than part of the map field.

Fix the upstream MAP4 immediate sizing while porting: non-MAP4 VEX/EVEX
instructions keep mandatory-prefix sizing, but APX EVEX MAP4 preserves
OSIZE semantics so EVEX.pp=01 with W=0 can select nFixedSize16 instead
of over-consuming the next instruction bytes.
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2 participants