Add pcb-layout-design reasoning protocol#179
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Alan-Jowett merged 5 commits intomicrosoft:mainfrom Apr 6, 2026
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Add a systematic reasoning protocol for PCB layout and routing from a completed schematic. This is Step 3 of 9 in the end-to-end hardware design workflow. The protocol covers 10 phases: 1. Input validation (schematic, footprints, design constraints) 2. Layout requirements gathering (interactive — connector placement, board size, mechanical constraints from user) 3. Board definition (outline, layer stackup for 2-layer and 4-layer) 4. Design rule configuration (net classes, trace widths, clearances matched to target fab house) 5. Component placement strategy (priority ordering, thermal, DFM) 6. Routing strategy (net priorities, impedance control, ground planes) 7. Python script generation (pcbnew API — board setup, placement, design rules, DSN export) 8. Autorouting execution (FreeRouting headless, SES import, zone fills) 9. DRC validation loop (kicad-cli DRC, error classification, automated fix with max 5 iterations) 10. Self-audit checklist cross-referencing layout-design-review Key design decisions: - Python pcbnew API approach instead of raw .kicad_pcb S-expression generation. PCB routing is a geometric optimization problem that LLMs cannot solve by generating coordinates directly. The script approach is deterministic, reviewable, and delegates routing to FreeRouting (a proper autorouter). - Interactive Phase 2 gathers user spatial preferences (connector edges, component positions, mechanical constraints) before any design decisions are made. - Complete automated loop: generate -> route -> validate -> fix, with max 5 iterations before escalating to user. - Pairs with existing layout-design-review for adversarial audit. Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>
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Pull request overview
Adds a new PromptKit reasoning protocol to guide generating a KiCad PCB layout (placement + autorouting + DRC loop) from a completed schematic, aligning with the repo’s hardware design workflow progression (Step 3 of 9).
Changes:
- Introduces
pcb-layout-designreasoning protocol with phased layout requirements gathering, board definition, routing strategy, and DRC iteration guidance. - Registers the new protocol in
manifest.yamlunder reasoning protocols.
Reviewed changes
Copilot reviewed 2 out of 2 changed files in this pull request and generated 2 comments.
| File | Description |
|---|---|
| protocols/reasoning/pcb-layout-design.md | New reasoning protocol describing an automated KiCad pcbnew + FreeRouting + DRC workflow for PCB layout generation. |
| manifest.yaml | Adds the new reasoning protocol entry so it can be discovered/assembled by the bootstrap engine. |
Address two reviewer findings: 1. Invalid kicad-cli command: 'kicad-cli pcb new -o board.kicad_pcb' is not a valid or portable KiCad CLI subcommand. Replaced with the standard workflow: user runs 'Update PCB from Schematic' in KiCad to populate the .kicad_pcb with footprints and nets, then the script loads it via pcbnew.LoadBoard(). 2. Missing board population step: The script template showed placement and routing on a 'board' object but never explained how it gets populated with footprints and nets from the schematic. Added an explicit 'Board loading prerequisite' section (new step 2) documenting the required workflow and the pcbnew.LoadBoard() call. Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>
1. High-Speed net class via size 0.4/0.2mm had a 0.2mm drill which is below the standard fab minimum of 0.3mm (JLCPCB, PCBWay). Changed to 0.6/0.3mm to match standard services. Added note that smaller vias require HDI/microvia fab capability. 2. Duplicate item numbering in Phase 7: two items both numbered '4' (Configuration section and Error handling). Renumbered Error handling to '5'. Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>
1. board.Save('board.kicad_pcb') was hardcoded but the script takes
the board path as sys.argv[1]. Changed to save back to the input
path for consistency.
2. Error handling referenced 'netlist import failures' and 'missing
footprint libraries' but the script loads a pre-populated
.kicad_pcb (no netlist import). Updated error cases to match the
actual workflow: invalid path, LoadBoard failures, missing
footprints/nets, DSN/SES export/import failures.
Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>
…fest 1. Script example crashed with IndexError when run without arguments. Added arg count check, usage message, and try/except around LoadBoard to match the error handling requirements in step 5. 2. Manifest description omitted '2-layer and 4-layer stackups' which the protocol frontmatter includes. Added to manifest for discoverability. Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>
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Summary
Add a \pcb-layout-design\ reasoning protocol for PCB layout and routing from a completed schematic. This is Step 3 of 9 in building the end-to-end hardware design workflow. It is the generative counterpart to the existing \layout-design-review\ analysis protocol.
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