Add M-tile loop with dispatch capping for Intel Xe2/3-LPG

[jchen10]

• Wrap 8x16x16 MatMulNBits(SubgroupMatrix) kernel body in M-tile loop using uniforms.m_tiles_per_wg for tile assignment per workgroup
• Cap dispatch_y on Xe2/3-LPG when M > 2k, with occupancy factor 16x
• Non-Intel or small-M paths pass m_tiles_per_wg=1 (no behavior change)

[jchen10]

We observed a sharp perf drop of prefill for long prompts(>4k) on PTL. This PR can largely alleviate the problem.

@qjia7 @guschmue PTAL

[Copilot]

Pull request overview

This PR updates the WebGPU SubgroupMatrix MatMulNBits 8x16x16 path to reduce dispatch overhead on large-M Intel Xe2/Xe3-LPG devices by having each workgroup process multiple M-tiles sequentially, driven by a new m_tiles_per_wg uniform and a capped dispatch_y.

Changes:

• Wrap the 8x16x16 WGSL kernel body in an outer M-tile loop controlled by uniforms.m_tiles_per_wg.
• Add m_tiles_per_wg to the program’s uniform interface and pass it from the CPU side.
• Cap dispatch_y for large M on Intel Xe2/Xe3-LPG and derive m_tiles_per_wg accordingly.

Reviewed changes

Copilot reviewed 3 out of 3 changed files in this pull request and generated 1 comment.

File	Description
onnxruntime/contrib_ops/webgpu/quantization/subgroup_matrix_matmul_nbits_8x16x16.wgsl.template	Adds an outer M-tile loop and resets accumulators per tile using m_tiles_per_wg.
onnxruntime/contrib_ops/webgpu/quantization/subgroup_matrix_matmul_nbits.h	Extends the uniform variable list with m_tiles_per_wg.
onnxruntime/contrib_ops/webgpu/quantization/subgroup_matrix_matmul_nbits.cc	Computes capped dispatch_y on Intel Xe2/Xe3-LPG and passes m_tiles_per_wg to the shader.

---

💡 Add Copilot custom instructions for smarter, more guided reviews. Learn how to get started.