Aegis is a fully open-source FPGA, from the silicon up.
Open-source FPGA efforts have made huge strides: projects like Project IceStorm and Apicula reverse-engineer proprietary bitstream formats, OpenFPGA and FABulous generate open FPGA fabric from architecture descriptions, and Cologne Chip's GateMate ships a commercial FPGA with a fully open-source toolchain. Where these projects each tackle a piece of the puzzle, Aegis is a full-stack, end-to-end open-source FPGA: fabric generation, synthesis, place-and-route, bitstream packing, simulation, and tapeout all live in one project, designed from the ground up for open source. From HDL to GDS, nothing is behind a proprietary wall.
The project generates parameterized FPGA devices with LUT4, BRAM, DSP, SerDes, and clock management tiles, along with everything needed to synthesize user designs onto them and tape out the fabric itself to a foundry via open PDKs and shuttle services like wafer.space.
The first Aegis device, targeting GF180MCU via wafer.space.
| Resource | Count |
|---|---|
| LUT4 | ~2880 |
| BRAM (128x8) | 128 tiles |
| DSP18 (18x18 MAC) | 64 tiles |
| I/O pads | 224 |
| SerDes | 4 |
| Clock tiles | 2 (8 outputs) |
| Routing tracks | 4 per edge |
nix build .#terra-1 # Generate IP (SV, JSON, chipdb, techmap)
nix build .#terra-1-tapeout # Full RTL-to-GDS for fab submissionEach device gets a complete FPGA toolchain via the tools output:
# Synthesize a Verilog design to Aegis cells
yosys -c synth.tcl # using $tools/share/yosys/aegis/*_cells.v + *_techmap.v
# Place and route on the fabric
nextpnr-aegis-terra_1 --json design_mapped.json --write design_pnr.json
# Pack into a bitstream
terra_1-pack --pnr design_pnr.json --output design.bin
# Simulate with the bitstream loaded
terra_1-sim --bitstream design.bin --cycles 1000 --vcd waves.vcdThe tapeout pipeline synthesizes the FPGA fabric itself to PDK standard cells:
nix build .#terra-1-tapeout
ls result/
# terra_1_synth.v — gate-level netlist (Yosys)
# terra_1_final.def — placed & routed layout (OpenROAD)
# terra_1.gds — GDS2 for fab submission
# terra_1_layout.png — layout render
# timing.rpt — timing analysis
# power.rpt — power reportSupports GF180MCU (wafer.space) and Sky130 PDKs.
Requires Nix with flakes enabled.
# Build the default package (aegis-ip-tools)
nix build
# Build Terra 1 IP
nix build .#terra-1
# Run the blinky example as a check
nix build .#checks.$(nix eval --raw nixpkgs#system).terra-1-blinky
# Enter development shell
nix developThe FPGA fabric is generated by ROHD (a Dart HDL framework) and outputs synthesizable SystemVerilog. The architecture follows Xilinx-style conventions:
- CLB: LUT4 + D flip-flop + MUXCY carry chain (18-bit config)
- Tile: CLB + 4-directional routing muxes (46-bit config)
- BRAM: Dual-port 128x8 block RAM (8-bit config)
- DSP: 18x18 multiply-accumulate with optional pipeline (16-bit config)
- IO: Bidirectional pad with input/output registers (8-bit config)
- SerDes: Protocol-agnostic serializer/deserializer (32-bit config)
- Clock: 4-output clock divider with phase control (49-bit config)
Configuration is loaded via a serial shift register chain: clock tiles -> IO tiles -> SerDes tiles -> fabric tiles (row-major).
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OpenFPGA — An open-source FPGA IP generator from the University of Utah. Given an XML architecture description, it generates synthesizable Verilog for a complete FPGA fabric along with bitstream tooling and self-testing infrastructure. Silicon-proven through DARPA's POSH program.
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FABulous — An open-source embedded FPGA (eFPGA) framework from the University of Manchester. Generates custom FPGA fabric from CSV-based configuration and integrates Yosys and nextpnr. Silicon-proven with 12+ tapeouts across nodes from TSMC 180nm down to 28nm CMOS.
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Cologne Chip GateMate — A commercial FPGA on GlobalFoundries 28nm with a fully open-source, license-free toolchain built on Yosys, nextpnr, and openFPGALoader. The silicon itself is proprietary, but it is notable as one of the few commercial FPGAs to embrace open-source EDA tools end-to-end.
