Add Support for Generate Expressions by Morgan2010 · Pull Request #21 · mipalgu/VHDLParsing

Morgan2010 · 2023-09-18T04:12:17Z

This PR adds support for defining generate expressions. The only supported expression at the moment is the for-generate expression, e.g.

<label>: for <iterator> in <range> generate
    <body>
end generate <label>;

Morgan2010 added 13 commits September 17, 2023 00:11

Created first version of ForGenerate statement.

174380e

Fixed errors in rawValue.

debc210

Created basic init that parses vhdl code for ForGenerate statments.

e6d7943

Created generate block for supporting future generate statements.

5ccefdb

Finished tests for ForGenerate.

f72af70

Added documentation.

99b57c7

Added ForGenerate to documentation.

ea47a3a

Incorporated GenerateBlock into AsynchronousBlock.

cd06d98

Finished GenerateBlock.

4ceeb18

Added more tests.:

3875f8d

Incorporated Generate statements into AsynchronousBlock.

9bd52bb

Disabled file_length for string extension.

0117a54

Add GenerateBlock to documentation.

2d985f0

Morgan2010 merged commit 66f7af5 into main Sep 18, 2023

Morgan2010 deleted the generate branch September 18, 2023 04:24

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