GitHub - mitulty/multi_cycle_processor: Design of a multi-cycle processor based on IITB RISC ISA

Instruction Set

This is the assembler that converts assembly code to machine readable bit stream that can be used to initialise the instruction ROM.

takes assembly code file as input:

python getprogram.py <path-to-program.txt>

Note: Assembler assumes the correctness of syntax of assembly code provided.

Name		Name	Last commit message	Last commit date
Latest commit History 3 Commits
Assembly_Codes		Assembly_Codes
doc/images		doc/images
Big_MUX.vhd		Big_MUX.vhd
LICENSE		LICENSE
MUX_PE.vhd		MUX_PE.vhd
README.md		README.md
alu.vhd		alu.vhd
comp.vhd		comp.vhd
controller.v		controller.v
cpu.vhd		cpu.vhd
datapath.vhd		datapath.vhd
getprogram.py		getprogram.py
mypkg.vhd		mypkg.vhd
pc_incrementer.vhd		pc_incrementer.vhd
pcplusone.vhd		pcplusone.vhd
priority_encoder.vhd		priority_encoder.vhd
proc_multicycle.vhd		proc_multicycle.vhd
proc_multicycle_tb.vhd		proc_multicycle_tb.vhd
program.txt		program.txt
ram.txt		ram.txt
ram.v		ram.v
reg_1bit.vhd		reg_1bit.vhd
reg_Nbit.vhd		reg_Nbit.vhd
register_file.vhd		register_file.vhd
rom.txt		rom.txt
rom.v		rom.v