PORT interrupt handling, reading LATCH persists previous value

[natersoz]

This is probably related to the Nordic errata:

     * Errata nRF52832 Rev2, v1.0 3.44 [173]
     * GPIO: Writes to LATCH register take several CPU cycles to take effect
     * Conditions:   Reading the LATCH register right after writing to it.
     * Consequences: Old value of the LATCH register is read.
     * Workaround:   Have at least 3 CPU cycles of delay between the write
     *               and the subsequent read to the LATCH register.
     *               This can be achieved by having 3 dummy reads to the
     *               LATCH register.

The LATCH set of bits contains the bit from the previous interrupt.

[natersoz]

I've found a work around for this which is now in master.
A better solution would be nice.