RT Transmitter and Receiver

This project implements and verifies a UART (Universal Asynchronous Receiver Transmitter) protocol in Verilog HDL. The design includes a UART transmitter, receiver, and baud rate generator operating at 2400 baud with an 8-bit data width. Functional verification is performed using a structured testbench consisting of reference models, loopback configuration, driver, and scoreboard. Various directed testcases such as alternating patterns, boundary values, walking ones, continuous transmission, and reset conditions were verified using Questa SIM and Vivado.