Control-Bounded A/D Conversion (cbadc) Toolbox

This package is intended as a design tool for aiding the construction of control-bounded A/D converters. Specifically, it is capable of:

• Generating transfer functions for analog systems and/or digital estimator parametrizations.
• Estimating samples from control signals.
• Simulating analog system and digital control interactions.

Documentation

The projects official documentation can be found at Read the Docs.

Background & References

For a in depth description of the control-bounded conversion concept consider the following publications

• Control-bounded analog-to-digital conversion, circuits, systems, and signal processing, 2021
• Control-bounded converters, PhD Thesis, 2020.
• Control-bounded analog-to-digital conversion: transfer functions analysis, proof of concept, and digital filter implementation, arXiv:2001.05929, 2020
• Control-based analog-to-digital conversion without sampling and quantization, information theory & applications workshop, 2015
• Analog-to-digital conversion using unstable filters, information theory & applications workshop, 2011

Installation

Install cbadc by typing

pip install cbadc

into your console. Note that, currently cbadc is only supported for Python3.8 and later.

Source Code

The source code is hosted on https://github.com/hammal/cbadc.

Bugs and Issues

Please report problems at https://github.com/hammal/cbadc/issues

Changelog

0.2.0

Major structural changes. Mainly motivated by improving simulators and filter coefficient computations to support switch-cap digital control simulations.

Specifically,

• digital clock to aid the simulator and digital estimator computation
• digital control and derived classes have a new interface to support digital clock, i.e, DigitalControl(..., clock, ...).
• Simulator
  • Analytical simulator implemented using SymPy
  • Mpmath simulator implemented using mpmath
  • Two Numerical simulators implemented using NumPy
    • Full simulator the pervious default simulator.
    • pre-computed simulator same as Full simulator with the distinction that the control contributions are pre-computed.
  • The previous default StateSpaceSimulator class has been replaced by the get_simulator function. The simulation backend is chosen by passing an instance of SimulatorType.
  • The simulation clock period Ts is replaced by the digital clock object and thus all simulator classes and the factory function get_simulation(..., clock, ...) is now instantiated with a clock determining the sample times.
• DigitalEstimator
  • The default DigitalEstimator changes it's name to BatchEstimator
  • an additional filter computation backend implemented with mpmath
• Improved care implementation using SymPy instead of SciPy.
• cbadc.specification.get_chain_of_integrator and cbadc.specification.get_leap_frog a computation aid to dimension chain-of-integrators and leap-frog analog-frontends to meet ENOB and BW specifications

Added verilog-ams circuit-level submodule

Such that circuit-level implementations can be

• constructed in Verilog-ams
• the resulting filter coefficients can be computed
• the resulting analog frontends can be simulated.

0.1.5

Added figures of merit fom modul, MurmannSurvey convenience class, and a new tutorial The Murmann ADC Survey.

0.1.2

Added fixed point arithmetics for FIR filter implementation.

0.1.1

Added support for switched capacitor digital control by adding a new:

• simulator,
• digital control,
• and modifications to the FIR digital estimator to handle the switch cap case.

0.1.0

• First public release