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@timonix timonix commented Dec 9, 2025

Why:
The integer type shows up as an std_logic array in the waveform viewer. But its always parsed with the lowest number of bits, basically guaranteeing that it ends up as a negative number.

The GHDL simulator (and many others) always uses 32 bit signed integers, regardless of the range set in the code.

In this very basic entity generates a single signal which should have the signed/unsigned value of 1.
But instead get the waveform will show -1 when using signed, despite the integer range allowing negative numbers.

entity s is
end entity s;

architecture rtl of s is
    signal A : integer range -16 to 16 := 1;
begin
end architecture;

How:
I made the parsing arrays match the bit width field when there is a mismatch. So integers are now 32 bit arrays and will correctly show up in the waveform viewer.

@hendrikmennen
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Thank you!

@hendrikmennen hendrikmennen merged commit 69da8e3 into one-ware:main Dec 10, 2025
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2 participants