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FPGA: Reduce the design size of the memory_attributes design in simulation #1383

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Feb 27, 2023
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FPGA: Reduce the design size of the memory_attributes design in simulation #1383

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5 changes: 5 additions & 0 deletions ...ctProgramming/C++SYCL_FPGA/Tutorials/Features/memory_attributes/src/memory_attributes.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -12,7 +12,12 @@ using namespace sycl;

// constants for this tutorial
constexpr size_t kRows = 8;
#if defined(FPGA_SIMULATOR)
// Use a smaller unroll factor when running simulation
constexpr size_t kVec = 1;
#else
constexpr size_t kVec = 4;
#endif
constexpr size_t kMaxVal = 512;
constexpr size_t kNumTests = 64;
constexpr size_t kMaxIter = 8;
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