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FPGA: Update seeds of the GZIP and QRD design to meet performance target #1414

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Merged
merged 1 commit into from
Mar 9, 2023
Merged

FPGA: Update seeds of the GZIP and QRD design to meet performance target #1414

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4 changes: 2 additions & 2 deletions DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/gzip/src/CMakeLists.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -74,10 +74,10 @@ elseif(DEVICE_FLAG MATCHES "S10")
# S10 parameters
set(NUM_ENGINES 2)
if(DEFINED LOW_LATENCY)
set(SEED "-Xsseed=16")
set(SEED "-Xsseed=2")
set(NUM_REORDER "")
else()
set(SEED "-Xsseed=1")
set(SEED "-Xsseed=10")
# For the High Bandwidth variant, specify 6 reordering units to improve global memory read bandwidth across 4 channels of DDR.
# For Low Latency variant this is not necessary since only one channel of global memory is used (host memory).
set(NUM_REORDER "-Xsnum-reorder=6")
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4 changes: 2 additions & 2 deletions DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/qrd/src/CMakeLists.txt
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Expand Up @@ -64,15 +64,15 @@ if(DEVICE_FLAG MATCHES "A10")
set(COMPLEX 1)
set(FIXED_ITERATIONS 64)
set(CLOCK_TARGET "-Xsclock=360MHz")
set(SEED "-Xsseed=7")
set(SEED "-Xsseed=1")
elseif(DEVICE_FLAG MATCHES "S10")
# S10 parameters
set(ROWS_COMPONENT 256)
set(COLS_COMPONENT 256)
set(COMPLEX 1)
set(FIXED_ITERATIONS 110)
set(CLOCK_TARGET "-Xsclock=480MHz")
set(SEED "-Xsseed=2")
set(SEED "-Xsseed=3")
elseif(DEVICE_FLAG MATCHES "Agilex")
# Agilex™ parameters
set(ROWS_COMPONENT 256)
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