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Expand Up @@ -21,6 +21,9 @@ This FPGA tutorial demonstrates how to build SYCL device libraries from RTL sour
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> :warning: Make sure you add the device files associated with the FPGA that you are targeting to your Intel® Quartus® Prime installation.


> :warning: When targeting an IP-only flow, the RTL library feature will not work when compiling to Quartus and will error out in the late-stage compile. RTL libraries will work in the simulation flow. This will be fixed in a future release. This is documented in the [compiler release notes](https://www.intel.com/content/www/us/en/developer/articles/release-notes/intel-oneapi-dpc-c-compiler-release-notes.html).

## Prerequisites

This sample is part of the FPGA code samples.
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