@@ -2109,6 +2109,183 @@ static const char ** dqSiteMap_rcB4
21092109 },
21102110};
21112111
2112+ //##############################################################################
2113+ // DRAM site tables for RAW CARD C4
2114+ //##############################################################################
2115+
2116+ static const char * dramSiteCardC4PortARank04 [] =
2117+ {
2118+ "DA12.d0" , "DA12.d1" , "DA12.d2" , "DA12.d3" ,
2119+ "DA02.d1" , "DA02.d0" , "DA02.d3" , "DA02.d2" ,
2120+
2121+ "DA05.d1" , "DA05.d0" , "DA05.d2" , "DA05.d3" ,
2122+ "DA15.d1" , "DA15.d2" , "DA15.d3" , "DA15.d0" ,
2123+
2124+ "DA17.d3" , "DA17.d1" , "DA17.d2" , "DA17.d0" ,
2125+ "DA07.d0" , "DA07.d2" , "DA07.d1" , "DA07.d3" ,
2126+
2127+ "DA18.d2" , "DA18.d1" , "DA18.d3" , "DA18.d0" ,
2128+ "DA06.d1" , "DA06.d2" , "DA06.d3" , "DA06.d0" ,
2129+
2130+ "DA03.d1" , "DA03.d3" , "DA03.d2" , "DA03.d0" ,
2131+ "DA13.d3" , "DA13.d2" , "DA13.d1" , "DA13.d0" ,
2132+
2133+ "DA16.d0" , "DA16.d2" , "DA16.d1" , "DA16.d3" ,
2134+ "DA08.d2" , "DA08.d3" , "DA08.d0" , "DA08.d1" ,
2135+
2136+ "DA14.d3" , "DA14.d0" , "DA14.d2" , "DA14.d1" ,
2137+ "DA04.d0" , "DA04.d3" , "DA04.d2" , "DA04.d1" ,
2138+
2139+ "DA09.d1" , "DA09.d2" , "DA09.d3" , "DA09.d0" ,
2140+ "DA19.d0" , "DA19.d3" , "DA19.d2" , "DA19.d1" ,
2141+
2142+ "DA01.d2" , "DA01.d1" , "DA01.d3" , "DA01.d0" ,
2143+ "DA11.d1" , "DA11.d3" , "DA11.d0" , "DA11.d2" ,
2144+
2145+ "DA1SP.d2" , "DA1SP.d3" , "DA1SP.d0" , "DA1SP.d1" ,
2146+ "" , "" , "" , "" ,
2147+ };
2148+
2149+ //------------------------------------------------------------------------------
2150+
2151+ static const char * dramSiteCardC4PortBRank04 [] =
2152+ {
2153+ "DB08.d1" , "DB08.d0" , "DB08.d2" , "DB08.d3" ,
2154+ "DB18.d3" , "DB18.d2" , "DB18.d0" , "DB18.d1" ,
2155+
2156+ "DB12.d3" , "DB12.d0" , "DB12.d2" , "DB12.d1" ,
2157+ "DB02.d0" , "DB02.d3" , "DB02.d2" , "DB02.d1" ,
2158+
2159+ "DB04.d1" , "DB04.d3" , "DB04.d2" , "DB04.d0" ,
2160+ "DB14.d0" , "DB14.d2" , "DB14.d1" , "DB14.d3" ,
2161+
2162+ "DB13.d2" , "DB13.d0" , "DB13.d3" , "DB13.d1" ,
2163+ "DB03.d0" , "DB03.d1" , "DB03.d2" , "DB03.d3" ,
2164+
2165+ "DB17.d0" , "DB17.d2" , "DB17.d1" , "DB17.d3" ,
2166+ "DB07.d1" , "DB07.d0" , "DB07.d3" , "DB07.d2" ,
2167+
2168+ "DB05.d1" , "DB05.d0" , "DB05.d3" , "DB05.d2" ,
2169+ "DB15.d0" , "DB15.d2" , "DB15.d1" , "DB15.d3" ,
2170+
2171+ "DB09.d2" , "DB09.d1" , "DB09.d3" , "DB09.d0" ,
2172+ "DB19.d2" , "DB19.d0" , "DB19.d1" , "DB19.d3" ,
2173+
2174+ "DB01.d1" , "DB01.d3" , "DB01.d0" , "DB01.d2" ,
2175+ "DB11.d0" , "DB11.d3" , "DB11.d2" , "DB11.d1" ,
2176+
2177+ "DB06.d2" , "DB06.d0" , "DB06.d1" , "DB06.d3" ,
2178+ "DB16.d3" , "DB16.d1" , "DB16.d2" , "DB16.d0" ,
2179+
2180+ "DB1SP.d2" , "DB1SP.d3" , "DB1SP.d1" , "DB1SP.d0" ,
2181+ "" , "" , "" , "" ,
2182+ };
2183+
2184+ //------------------------------------------------------------------------------
2185+
2186+ static const char * dramSiteCardC4PortCRank04 [] =
2187+ {
2188+ "DC13.d1" , "DC13.d3" , "DC13.d0" , "DC13.d2" ,
2189+ "DC03.d0" , "DC03.d2" , "DC03.d3" , "DC03.d1" ,
2190+
2191+ "DC04.d1" , "DC04.d2" , "DC04.d3" , "DC04.d0" ,
2192+ "DC14.d1" , "DC14.d3" , "DC14.d0" , "DC14.d2" ,
2193+
2194+ "DC06.d0" , "DC06.d3" , "DC06.d1" , "DC06.d2" ,
2195+ "DC16.d2" , "DC16.d0" , "DC16.d3" , "DC16.d1" ,
2196+
2197+ "DC09.d3" , "DC09.d2" , "DC09.d1" , "DC09.d0" ,
2198+ "DC19.d1" , "DC19.d0" , "DC19.d3" , "DC19.d2" ,
2199+
2200+ "DC12.d2" , "DC12.d0" , "DC12.d3" , "DC12.d1" ,
2201+ "DC02.d3" , "DC02.d1" , "DC02.d2" , "DC02.d0" ,
2202+
2203+ "DC17.d2" , "DC17.d0" , "DC17.d1" , "DC17.d3" ,
2204+ "DC07.d3" , "DC07.d1" , "DC07.d0" , "DC07.d2" ,
2205+
2206+ "DC05.d1" , "DC05.d3" , "DC05.d2" , "DC05.d0" ,
2207+ "DC15.d2" , "DC15.d0" , "DC15.d3" , "DC15.d1" ,
2208+
2209+ "DC01.d0" , "DC01.d3" , "DC01.d2" , "DC01.d1" ,
2210+ "DC11.d3" , "DC11.d0" , "DC11.d1" , "DC11.d2" ,
2211+
2212+ "DC08.d1" , "DC08.d3" , "DC08.d2" , "DC08.d0" ,
2213+ "DC18.d0" , "DC18.d2" , "DC18.d1" , "DC18.d3" ,
2214+
2215+ "DC1SP.d3" , "DC1SP.d0" , "DC1SP.d1" , "DC1SP.d2" ,
2216+ "" , "" , "" , "" ,
2217+ };
2218+
2219+ //------------------------------------------------------------------------------
2220+
2221+ static const char * dramSiteCardC4PortDRank04 [] =
2222+ {
2223+ "DD06.d2" , "DD06.d1" , "DD06.d0" , "DD06.d3" ,
2224+ "DD16.d3" , "DD16.d2" , "DD16.d0" , "DD16.d1" ,
2225+
2226+ "DD05.d1" , "DD05.d3" , "DD05.d2" , "DD05.d0" ,
2227+ "DD15.d2" , "DD15.d0" , "DD15.d3" , "DD15.d1" ,
2228+
2229+ "DD13.d3" , "DD13.d0" , "DD13.d1" , "DD13.d2" ,
2230+ "DD03.d1" , "DD03.d3" , "DD03.d2" , "DD03.d0" ,
2231+
2232+ "DD09.d3" , "DD09.d1" , "DD09.d2" , "DD09.d0" ,
2233+ "DD19.d0" , "DD19.d2" , "DD19.d1" , "DD19.d3" ,
2234+
2235+ "DD12.d2" , "DD12.d1" , "DD12.d3" , "DD12.d0" ,
2236+ "DD02.d0" , "DD02.d2" , "DD02.d3" , "DD02.d1" ,
2237+
2238+ "DD18.d1" , "DD18.d3" , "DD18.d0" , "DD18.d2" ,
2239+ "DD08.d0" , "DD08.d2" , "DD08.d3" , "DD08.d1" ,
2240+
2241+ "DD04.d0" , "DD04.d1" , "DD04.d3" , "DD04.d2" ,
2242+ "DD14.d2" , "DD14.d0" , "DD14.d3" , "DD14.d1" ,
2243+
2244+ "DD11.d0" , "DD11.d2" , "DD11.d1" , "DD11.d3" ,
2245+ "DD01.d1" , "DD01.d3" , "DD01.d0" , "DD01.d2" ,
2246+
2247+ "DD17.d3" , "DD17.d0" , "DD17.d1" , "DD17.d2" ,
2248+ "DD07.d2" , "DD07.d1" , "DD07.d3" , "DD07.d0" ,
2249+
2250+ "DD1SP.d1" , "DD1SP.d3" , "DD1SP.d2" , "DD1SP.d0" ,
2251+ "" , "" , "" , "" ,
2252+ };
2253+
2254+ //------------------------------------------------------------------------------
2255+
2256+ static const char * * dqSiteMap_rcC4
2257+ [MAX_MBA_PER_MEMBUF ][PORT_SLCT_PER_MBA ][MASTER_RANKS_PER_MBA ] =
2258+ {
2259+ { // MBA 0
2260+ { // Port 0
2261+ dramSiteCardC4PortARank04 , NULL , // Ranks 0-1
2262+ NULL , NULL , // Ranks 2-3
2263+ dramSiteCardC4PortARank04 , NULL , // Ranks 4-5
2264+ NULL , NULL , // Ranks 6-7
2265+ },
2266+ { // Port 1
2267+ dramSiteCardC4PortBRank04 , NULL , // Ranks 0-1
2268+ NULL , NULL , // Ranks 2-3
2269+ dramSiteCardC4PortBRank04 , NULL , // Ranks 4-5
2270+ NULL , NULL , // Ranks 6-7
2271+ },
2272+ },
2273+ { // MBA 1
2274+ { // Port 0
2275+ dramSiteCardC4PortCRank04 , NULL , // Ranks 0-1
2276+ NULL , NULL , // Ranks 2-3
2277+ dramSiteCardC4PortCRank04 , NULL , // Ranks 4-5
2278+ NULL , NULL , // Ranks 6-7
2279+ },
2280+ { // Port 1
2281+ dramSiteCardC4PortDRank04 , NULL , // Ranks 0-1
2282+ NULL , NULL , // Ranks 2-3
2283+ dramSiteCardC4PortDRank04 , NULL , // Ranks 4-5
2284+ NULL , NULL , // Ranks 6-7
2285+ },
2286+ },
2287+ };
2288+
21122289//##############################################################################
21132290// DRAM site tables for RAW CARD D4
21142291//##############################################################################
@@ -2499,6 +2676,14 @@ int32_t getDramSiteInfo( uint8_t i_cardType, uint8_t i_mbaPos,
24992676 o_dramMap = dramSiteMap_rcB [i_mbaPos ][i_ps ][i_mrank ];
25002677 break ;
25012678
2679+ case CEN_TYPE_C4 :
2680+ o_x4Dram = true;
2681+ o_cardName = "RAW_CARD_C4 " ;
2682+ o_dqMap = dqSiteMap_rcC4 [i_mbaPos ][i_ps ][i_mrank ];
2683+ // We can use the same dram Mapping as a similar card
2684+ o_dramMap = dramSiteMap_rcC [i_mbaPos ][i_ps ][i_mrank ];
2685+ break ;
2686+
25022687 case CEN_TYPE_D4 :
25032688 o_x4Dram = true;
25042689 o_cardName = "RAW_CARD_D4 " ;
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