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rlippertdcrowell77
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pnor: fix support for SP/BMC-less SFC init
also fixes up mismatched IDs for macronix flash parts Change-Id: I81b89e9a7239669e769864711797830b44351bfd Signed-off-by: Robert Lippert <rlippert@google.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/25020 Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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-29
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4 files changed

+38
-29
lines changed

‎src/usr/pnor/HBconfig‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -43,3 +43,9 @@ config PNOR_TWO_SIDE_SUPPORT
4343
depends on !PNOR_IS_32MB
4444
help
4545
This is used to turn on/off two sided pnor support
46+
47+
config PNOR_INIT_FOUR_BYTE_ADDR
48+
default n
49+
depends on !BMC_DOES_SFC_INIT
50+
help
51+
PNOR starts out in 3-byte address mode, hostboot must enable 4-byte mode.

‎src/usr/pnor/norflash.H‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@
55
/* */
66
/* OpenPOWER HostBoot Project */
77
/* */
8-
/* Contributors Listed Below - COPYRIGHT 2014 */
8+
/* Contributors Listed Below - COPYRIGHT 2014,2016 */
99
/* [+] Google Inc. */
1010
/* [+] International Business Machines Corp. */
1111
/* */
@@ -48,8 +48,8 @@ enum NorChipIDs
4848
MICRON_NOR_ID = 0x20ba2000, /**< Micron NOR */
4949

5050
MACRONIX_MFG_ID = 0xC2000000, /**< Macronix Mfg ID */
51-
MACRONIX32_NOR_ID = 0xC2201A00, /**< Macronix NOR MXxxL51235F */
52-
MACRONIX64_NOR_ID = 0xC2201900, /**< Macronix NOR MXxxL25635F */
51+
MACRONIX64_NOR_ID = 0xC2201A00, /**< Macronix NOR MXxxL51235F */
52+
MACRONIX32_NOR_ID = 0xC2201900, /**< Macronix NOR MXxxL25635F */
5353

5454
/* Note: Simics currently models Micron NOR */
5555
VPO_NOR_ID = 0x20201800, /**< VPO NOR chip ID */

‎src/usr/pnor/pnor_common.C‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -6,6 +6,7 @@
66
/* OpenPOWER HostBoot Project */
77
/* */
88
/* Contributors Listed Below - COPYRIGHT 2014,2016 */
9+
/* [+] Google Inc. */
910
/* [+] International Business Machines Corp. */
1011
/* */
1112
/* */
@@ -139,6 +140,11 @@ errlHndl_t PNOR::mmioToPhysicalOffset(uint64_t& o_hbbAddress)
139140
l_hbbMMIO = (l_hbbMMIO >> 32) & PNOR::LPC_TOP_OF_FLASH_OFFSET;
140141
o_hbbAddress = ((9*l_hbbMMIO) - (9*PNOR::LPC_SFC_MMIO_OFFSET)
141142
- PNOR::PNOR_SIZE) /8;
143+
#ifdef CONFIG_PNOR_INIT_FOUR_BYTE_ADDR
144+
// If the PNOR came up in 3-byte mode, then make sure to mask off
145+
// the address appropriately.
146+
o_hbbAddress &= 0x00ffffffu;
147+
#endif
142148
} while (0);
143149
return l_err;
144150
}

‎src/usr/pnor/sfc_ibm.C‎

Lines changed: 23 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -548,14 +548,6 @@ errlHndl_t SfcIBM::hwInit( )
548548
"SfcIBM::hwInit: iv_norChipId=0x%.8x> ",
549549
iv_norChipId );
550550

551-
//Query the configured size of the erase block
552-
l_err = readReg(SFC_CMD_SPACE,
553-
SFC_REG_ERASMS,
554-
iv_eraseSizeBytes);
555-
if(l_err) { break; }
556-
TRACFCOMP(g_trac_pnor,"iv_eraseSizeBytes=0x%X",iv_eraseSizeBytes);
557-
558-
559551
#ifndef CONFIG_BMC_DOES_SFC_INIT
560552
TRACFCOMP( g_trac_pnor, INFO_MRK "Initializing SFC registers" );
561553

@@ -603,27 +595,21 @@ errlHndl_t SfcIBM::hwInit( )
603595
//*** End Micron
604596
#endif
605597

606-
#ifdef CONFIG_RHESUS
607-
// HACK: Micron N25Q256A13 for use with EM100.
608-
{ 0x20ba1900, SFC_REG_CONF4, SPI_JEDEC_SECTOR_ERASE },
609-
{ 0x20ba1900, SFC_REG_CONF5, 4096 },
610-
#endif
611-
612598
#ifdef CONFIG_ALLOW_MACRONIX_PNOR
613599
//*** Macronix 512mb chip specific settings.
614-
{ PNOR::MACRONIX_NOR_ID, SFC_REG_SPICLK,
600+
{ PNOR::MACRONIX64_NOR_ID, SFC_REG_SPICLK,
615601
0 << SFC_REG_SPICLK_OUTDLY_SHFT |
616602
0 << SFC_REG_SPICLK_INSAMPDLY_SHFT |
617603
0 << SFC_REG_SPICLK_CLKHI_SHFT |
618604
0 << SFC_REG_SPICLK_CLKLO_SHFT
619605
},
620-
{ PNOR::MACRONIX_NOR_ID, SFC_REG_CONF8,
606+
{ PNOR::MACRONIX64_NOR_ID, SFC_REG_CONF8,
621607
2 << SFC_REG_CONF8_CSINACTIVEREAD_SHFT |
622608
8 << SFC_REG_CONF8_DUMMY_SHFT |
623609
SPI_JEDEC_FAST_READ << SFC_REG_CONF8_READOP_SHFT
624610
},
625-
{ PNOR::MACRONIX_NOR_ID, SFC_REG_CONF4, SPI_JEDEC_SECTOR_ERASE },
626-
{ PNOR::MACRONIX_NOR_ID, SFC_REG_CONF5, 4096 },
611+
{ PNOR::MACRONIX64_NOR_ID, SFC_REG_CONF4, SPI_JEDEC_SECTOR_ERASE },
612+
{ PNOR::MACRONIX64_NOR_ID, SFC_REG_CONF5, 4096 },
627613
//*** End Macronix
628614
#endif
629615
};
@@ -646,19 +632,30 @@ errlHndl_t SfcIBM::hwInit( )
646632
}
647633
if( l_err ) { break; }
648634

649-
#if 0 //@fixme-RTC:109860
650-
// Enable 4-byte addressing.
651-
l_err = SfcErrlFromRc( iv_sfc.set_4ba( &iv_sfc, 1 ) );
652-
if( l_err ) { break; }
635+
#ifdef CONFIG_PNOR_INIT_FOUR_BYTE_ADDR
636+
// Enable 4 byte addressing. This is safe even if 4BA is already
637+
// enabled by the BMC/FSP/etc.
638+
SfcCmdReg_t sfc_cmd;
639+
sfc_cmd.opcode = SFC_OP_START4BA;
640+
sfc_cmd.length = 0;
641+
l_err = writeReg(SFC_CMD_SPACE,
642+
SFC_REG_CMD,
643+
sfc_cmd.data32);
644+
if(l_err) { break; }
653645

654-
// Re-initialize internal erase size cached value.
655-
l_err = SfcErrlFromRc( iv_sfc.get_erase_size(
656-
&iv_sfc, &iv_eraseSizeBytes, NULL ) );
657-
if( l_err ) { break; }
646+
//Poll for complete status
647+
l_err = pollOpComplete();
648+
if(l_err) { break; }
658649
#endif
659650

660651
#endif //!CONFIG_BMC_DOES_SFC_INIT
661652

653+
//Query the configured size of the erase block
654+
l_err = readReg(SFC_CMD_SPACE,
655+
SFC_REG_ERASMS,
656+
iv_eraseSizeBytes);
657+
if(l_err) { break; }
658+
TRACFCOMP(g_trac_pnor,"iv_eraseSizeBytes=0x%X",iv_eraseSizeBytes);
662659

663660
#ifdef CONFIG_ALLOW_MICRON_PNOR
664661
if( iv_norChipId == PNOR::MICRON_NOR_ID )

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