Updated CVA6 Roadmap (markdown)
Improving DCLS
Update by project leads (not finished).
Per contributor's request
Completed with FPGA and SW plans.
Layout edit. Content unchanged.
First draft version of the roadmap.
Updated Performance Counters (markdown)
...and one more...
Missed a few...
A better way to highlight keywords with a preceding tick
Expanded description of CVA6 cfg generation
Use better macro expansion example
Add "macro expansion" sub-section
Cleanup
Update based on feedback from @cainria.
(1) Add license header, (2) Use SystemVerilog fenced code blocks.
Created Configuring SystemVerilog RTL Models (markdown)
Updated Home (markdown)
Coarse overview of PLIC memory map
Add table of performance counters
Initial Home page