8349582: APX NDD code generation for OpenJDK #23501

vamsi-parasa · 2025-02-06T20:26:49Z

The goal of this PR is to generate x86 code using Intel Advanced Performance Extensions (APX) instructions which doubles the number of general-purpose registers, from 16 to 32. Intel APX adds nondestructive destination (NDD) and no flags (NF) flavor for the scalar instructions through EVEX encoding.

For more information about APX, see https://www.intel.com/content/www/us/en/developer/articles/technical/advanced-performance-extensions-apx.html.

Progress

Change must be properly reviewed (1 review required, with at least 1 Reviewer)
Change must not contain extraneous whitespace
Commit message must refer to an issue

Issue

JDK-8349582: APX NDD code generation for OpenJDK (Sub-task - P4)

Reviewers

Jatin Bhateja (@jatin-bhateja - Reviewer) Review applies to e9369a40
Sandhya Viswanathan (@sviswa7 - Reviewer) Review applies to 51d0e0d4
Emanuel Peter (@eme64 - Reviewer)

Reviewing

Using git

Checkout this PR locally:
$ git fetch https://git.openjdk.org/jdk.git pull/23501/head:pull/23501
$ git checkout pull/23501

Update a local copy of the PR:
$ git checkout pull/23501
$ git pull https://git.openjdk.org/jdk.git pull/23501/head

Using Skara CLI tools

Checkout this PR locally:
$ git pr checkout 23501

View PR using the GUI difftool:
$ git pr show -t 23501

Using diff file

Download this PR as a diff file:
https://git.openjdk.org/jdk/pull/23501.diff

Using Webrev

Link to Webrev Comment

bridgekeeper · 2025-02-06T20:27:21Z

👋 Welcome back sparasa! A progress list of the required criteria for merging this PR into master will be added to the body of your pull request. There are additional pull request commands available for use with this pull request.

openjdk · 2025-02-06T20:28:06Z

@vamsi-parasa This change now passes all automated pre-integration checks.

ℹ️ This project also has non-automated pre-integration requirements. Please see the file CONTRIBUTING.md for details.

After integration, the commit message for the final commit will be:

8349582: APX NDD code generation for OpenJDK

Reviewed-by: epeter, jbhateja, sviswanathan

You can use pull request commands such as /summary, /contributor and /issue to adjust it as needed.

At the time when this comment was updated there had been 110 new commits pushed to the master branch:

7d1fe0e: 8339543: [vectorapi] laneHelper and withLaneHelper should be ForceInline
ddc4318: 8352628: Refine Grapheme test
d8c2f59: 8352064: AIX: now also able to build static-jdk image with a statically linked launcher
5709f79: 8352648: JFR: 'jfr query' should not be available in product builds
02a4ce2: 8352147: G1: TestEagerReclaimHumongousRegionsClearMarkBits test takes very long
de58009: 8351468: C2: array fill optimization assigns wrong type to intrinsic call
a875733: 8352486: [ubsan] compilationMemoryStatistic.cpp:659:21: runtime error: index 64 out of bounds for type const struct unnamed struct
5591f8a: 8351515: C2 incorrectly removes double negation for double and float
56a4ffa: 8352597: [IR Framework] test bug: TestNotCompilable.java fails on product build
e23e0f8: 8352591: Missing UnlockDiagnosticVMOptions in VerifyGraphEdgesWithDeadCodeCheckFromSafepoints test
... and 100 more: https://git.openjdk.org/jdk/compare/37ec796255ae857588a5c7e0d572407dd81cbec9...master

As there are no conflicts, your changes will automatically be rebased on top of these commits when integrating. If you prefer to avoid this automatic rebasing, please check the documentation for the /integrate command for further details.

As you do not have Committer status in this project an existing Committer must agree to sponsor your change. Possible candidates are the reviewers of this PR (@jatin-bhateja, @sviswa7, @eme64) but any other Committer may sponsor as well.

➡️ To flag this PR as ready for integration with the above commit message, type /integrate in a new comment. (Afterwards, your sponsor types /sponsor in a new comment to perform the integration).

openjdk · 2025-02-06T20:28:37Z

@vamsi-parasa The following label will be automatically applied to this pull request:

hotspot-compiler

When this pull request is ready to be reviewed, an "RFR" email will be sent to the corresponding mailing list. If you would like to change these labels, use the /label pull request command.

mlbridge · 2025-02-06T20:32:01Z

Webrevs

jatin-bhateja

Some initial comments.

jatin-bhateja · 2025-02-07T09:09:01Z

src/hotspot/cpu/x86/x86_64.ad

+  format %{ "eaddq    $dst, $src1, $src2\t# long ndd" %}
+  ins_encode %{
+    __ eaddq($dst$$Register, $src1$$Register, $src2$$Register, false);
+  %}


Your current scheme favors the emission of NDD instruction on APX-enabled targets, even if destination and source registers belong legacy GPR set. We should extend the assembler layer to demote EEVEX to REX encoding if dst matches with source operands.

FYI, the processor backend also uses Move Elimination to prevent the dispatch of GPR to GPR moves to execution ports.

This can be used to further break NDD patterns with all different legacy register operands, GPR to GPR moves should consume no more than 3 bytes encoding 1 byte for REX prefix, 1 for opcode, and 1 for ModRM byte, still less than 4 byte prefix.

By biasing the allocation of definition towards non-intersecting source operands, we can enhance the chances of EEVEX to REX demotions.

jatin-bhateja · 2025-02-07T09:09:33Z

src/hotspot/cpu/x86/x86_64.ad

+  predicate(UseAPX);
+  match(Set dst (AddL src1 src2));
+  effect(KILL cr);
+
+  format %{ "eaddq    $dst, $src1, $src2\t# long ndd" %}
+  ins_encode %{
+    __ eaddq($dst$$Register, $src1$$Register, $src2$$constant, false);
+  %}
+  ins_pipe( ialu_reg );
+%}
+
+instruct addL_rReg_mem_imm_ndd(rRegL dst, memory src1, immL32 src2, rFlagsReg cr)
+%{
+  predicate(UseAPX);
+  match(Set dst (AddL (LoadL src1) src2));
+  effect(KILL cr);
+
+  format %{ "eaddq    $dst, $src1, $src2\t# long ndd" %}


Can you kindly share the impact of adding all these new patterns on libjvm.so size ?

I am curious to know the amount of ADLC generated code for all these new patterns.

jatin-bhateja · 2025-02-07T09:12:43Z

src/hotspot/cpu/x86/x86_64.ad

+  int reg = ra_->get_encode(this);
+  if (reg > 15) {
+    return (offset < 0x80) ? 6 : 9; // REX2
+  } else {
+    return (offset < 0x80) ? 5 : 8; // REX
+  }


Please move this out to a separate patch.

Could you please create the PR as you identified and fixed this issue? I will remove this code block once your updated BoxLock node fix is integrated into the mainline.

src/hotspot/cpu/x86/x86_64.ad

jatin-bhateja · 2025-02-07T09:18:16Z

src/hotspot/cpu/x86/x86_64.ad

+  match(Set dst (CountTrailingZerosL (LoadL src)));
+  effect(KILL cr);
+
+  ins_cost(175);


Could you please let me know why you're using ins_cost here and not in above pattern?

sviswa7 · 2025-03-04T19:11:36Z

src/hotspot/cpu/x86/x86_64.ad

+    "eshrl    $dst, $mem, markWord::klass_shift_at_offset\t# compressed klass ptr, shifted (ndd)\n\t"
+  %}
+  ins_encode %{
+    __ eshrl($dst$$Register, $mem$$Address, markWord::klass_shift_at_offset, false);


This change could be done as part of loadNKlassCompactHeaders instruct itself as there is no additional register needed.
Something like below:
if (UseAPX_ {
__ eshrl($dst$$Register, $mem$$Address, markWord::klass_shift_at_offset, false);
} else {
__ movl($dst$$Register, $mem$$Address);
__ shrl($dst$$Register, markWord::klass_shift_at_offset);
}

Please see this suggestion incorporated in the updated code.

sviswa7 · 2025-03-04T19:22:55Z

src/hotspot/cpu/x86/x86_64.ad

+instruct countLeadingZerosI_nf(rRegI dst, rRegI src) %{
+  predicate(UseAPX && UseCountLeadingZerosInstruction);
+  match(Set dst (CountLeadingZerosI src));
+
+  format %{ "elzcntl  $dst, $src\t# count leading zeros (int  nf)" %}
+  ins_encode %{
+    __ elzcntl($dst$$Register, $src$$Register, true);
+  %}
+  ins_pipe(ialu_reg);
+%}
+


This instruct could be removed as this is already an unary operation with separate destination, Likewise other unary operator instructs could also be removed where the destination is already separate from source.

The ndd instructions epopcnt, elzcnt and etzcnt were removed as they have a separate destination. Please see the update code.

sviswa7 · 2025-03-04T19:27:02Z

src/hotspot/cpu/x86/x86_64.ad

@@ -5551,6 +5583,17 @@ instruct countLeadingZerosI_mem(rRegI dst, memory src, rFlagsReg cr) %{
  ins_pipe(ialu_reg_mem);
 %}

+instruct countLeadingZerosI_mem_nf(rRegI dst, memory src) %{
+  predicate(UseAPX && UseCountLeadingZerosInstruction);


This instruct could be removed as this is already an unary operation with separate destination,

Please see this suggestion incorporated in the updated code.

sviswa7 · 2025-03-05T18:00:44Z

test/hotspot/gtest/x86/x86-asmtest.py

+                # additional tests with rax as destination
+                if RegOp in [RegRegImmNddInstruction]:
+                    test_reg1 = 'rax'
+                    test_reg2 = random.choice(test_regs)


We don't need to generate another test_reg2, we could use the same from above. Thereby, we will not modify the existing tests and only have the new test instructions added in asmtest.out.h.

sviswa7 · 2025-03-05T18:21:00Z

src/hotspot/cpu/x86/x86_64.ad

  ins_pipe(ialu_reg);
 %}

+


A nit pick, unnecessary extra blank lines :).

Please see the additional blank lines removed in the updated code.

sviswa7 · 2025-03-05T18:27:22Z

src/hotspot/cpu/x86/x86_64.ad

+%}
+
+
 instruct cmovI_regUCF2_ne(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegI dst, rRegI src) %{


The cmovI_regUCF2_ne, cmovl_regUCF2_eq, cmovP_regUCF2_ne, cmovP_regUCF2_eq, cmovL_regUCF2_ne, cmovL_regUCF2_eq instructs could also use the ecmovl() instructions.

Please see the added NDD versions for cmovI_regUCF2_ne, cmovl_regUCF2_eq, cmovP_regUCF2_ne, cmovP_regUCF2_eq, cmovL_regUCF2_ne, cmovL_regUCF2_eq.

sviswa7 · 2025-03-05T19:21:27Z

src/hotspot/cpu/x86/x86_64.ad

+%{
+  predicate(UseAPX);
+  match(Set dst (AddI src1 src2));
+  effect(KILL cr);


We should also bring in the corresponding flag(PD::...); line from instruct addI_rReg in this and other rules where applicable.

Please see the updated code with flags(PD::...)

sviswa7 · 2025-03-05T23:29:07Z

src/hotspot/cpu/x86/x86_64.ad

  ins_pipe(ialu_reg);
 %}

+instruct negI_rReg_ndd(rRegI src, rRegI dst, immI_0 zero, rFlagsReg cr)


A nit pick in many of the new negI/negL instructs, we usually list the dst first in instruct.

Please see the order of dst and src fixed.

sviswa7 · 2025-03-05T23:48:05Z

src/hotspot/cpu/x86/x86_64.ad

 %}

+// Arithmetic Shift Right by variable
+instruct sarI_rReg_CL_ndd(rRegI dst, rRegI src, rcx_RegI shift, rFlagsReg cr)


The new instructs sarI_rReg_CL_ndd, shrI_rReg_CL_ndd, salL_rReg_CL_ndd, sarL_rReg_CL_ndd, shrL_rReg_CL_ndd could be removed and the original !bmi2 versions could be kept. We dont need to optimize with APX instructions for non bmi2 platforms.

Please see the updated code which removed NDD support for non bmi2 platforms.

sviswa7 · 2025-03-06T00:45:30Z

src/hotspot/cpu/x86/x86_64.ad

  ins_pipe(ialu_reg_mem);
 %}

+instruct andL_rReg_rReg_mem_ndd(rRegL dst, rRegL src1, memory src2, rFlagsReg cr)


It looks to me that we only need one of andL_rReg_rReg_mem_ndd & andL_rReg_mem_rReg_ndd as and is a commutative operator. Likewise for other commutative operators like or, add, xor, mul, etc.

sviswa7 · 2025-03-06T00:48:39Z

src/hotspot/cpu/x86/x86_64.ad

-// Or Instructions
-// Or Register with Register
-instruct orI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
+instruct orI_rReg_imm_rReg_ndd(rRegI dst, immI src1, rRegI src2, rFlagsReg cr)


It looks to me that we only need one of orI_rReg_rReg_imm_ndd or orI_rReg_imm_rReg_ndd as orI is a commutative operator.

After doing a quick test, it was noticed that both the rules (orI_rReg_rReg_imm and orI_rReg_imm_rReg) are needed to generate NDD instruction depending on the position of the immediate value.

sviswa7 · 2025-03-06T01:04:32Z

src/hotspot/cpu/x86/x86_64.ad

 instruct rorI_immI8_legacy(rRegI dst, immI8 shift, rFlagsReg cr)
 %{
-  predicate(!VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_INT);
+  predicate(!UseAPX && !VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_INT);


Don't need to change anything for non bmi2 platforms. The original predicate can be kept as is. This applies to all rorI, rolI, rorL, rolL.

Please see the updated code removing rorI, rolI, rorL, rolL for non bmi2 platforms.

sviswa7

Looks good to me.

vamsi-parasa · 2025-03-12T21:41:32Z

Hi Vladimir (@vnkozlov),

Could you please review this PR?

Thanks,
Vamsi

eme64

I had a quick look over this. It's a bit hard to review for me, because it is basically about specific APX instructions. We probably have to heavily rely on testing. But APX hardware is not yet available, right?

How can be best test this? Is there any way to emulate, maybe using SDE? What testing did you run for this?

eme64 · 2025-03-13T07:00:09Z

src/hotspot/cpu/x86/x86_64.ad

+  predicate(UseAPX);
+  match(Set dst (CMoveI (Binary cop cr) (Binary src1 src2)));
+
+  ins_cost(200); // XXX


What does the XXX stand for?

eme64 · 2025-03-13T07:03:32Z

src/hotspot/cpu/x86/x86_64.ad


+// Conditional move
+instruct cmovI_rReg_rReg_mem_ndd(rRegI dst, cmpOp cop, rFlagsReg cr, rRegI src1, memory src2)
+%{


Is this bracket usually not on the previous line?

eme64 · 2025-03-13T07:20:46Z

@vamsi-parasa I tried to launch testing, but my script fails because of some merge issue. Would you mind merging from master?

eme64 · 2025-03-24T07:49:41Z

@vamsi-parasa Testing looks good / no related test failures.

eme64 · 2025-03-21T09:27:54Z

test/hotspot/gtest/x86/x86-asmtest.py

 registers_mapping = {
    # skip rax, rsi, rdi, rsp, rbp as they have special encodings
-    # 'rax': {64: 'rax', 32: 'eax', 16: 'ax', 8: 'al'},
+    'rax': {64: 'rax', 32: 'eax', 16: 'ax', 8: 'al'},


You should probably update the copyright year, right?

Also: is this script ever run in testing? I didn't know we had python files in the repository 😅

eme64

I cannot really review he content, nor can I really test the APX features.
But I also cannot directly see any issues with it.

Therefore, I'll approve.
Once the hardware is available, we will probably discover some issues and have to fix them then.

Thanks @vamsi-parasa for the work!

vamsi-parasa · 2025-03-24T15:38:52Z

@vamsi-parasa Testing looks good / no related test failures.

Thank you very much Emanuel! (@eme64) :)

vamsi-parasa · 2025-03-24T15:50:40Z

I cannot really review he content, nor can I really test the APX features. But I also cannot directly see any issues with it.

Therefore, I'll approve. Once the hardware is available, we will probably discover some issues and have to fix them then.

Thanks @vamsi-parasa for the work!

Thank You Emanuel(@eme64) for doing the review, testing and approving the PR!

vamsi-parasa · 2025-03-24T15:51:58Z

/integrate

openjdk · 2025-03-24T15:52:29Z

@vamsi-parasa This pull request has not yet been marked as ready for integration.

test/hotspot/gtest/x86/x86-asmtest.py

Co-authored-by: Emanuel Peter <emanuel.peter@oracle.com>

eme64

Re-approved :)

vamsi-parasa · 2025-03-24T16:02:35Z

Re-approved :)

Thank you, Emanuel! :)

sviswa7 · 2025-03-24T16:36:28Z

/sponsor

openjdk · 2025-03-24T16:37:32Z

@sviswa7 The change author (@vamsi-parasa) must issue an integrate command before the integration can be sponsored.

vamsi-parasa · 2025-03-24T16:39:42Z

/integrate

openjdk · 2025-03-24T16:41:03Z

@vamsi-parasa
Your change (at version 06c52ce) is now ready to be sponsored by a Committer.

sviswa7 · 2025-03-24T16:41:47Z

/sponsor

openjdk · 2025-03-24T16:44:26Z

Going to push as commit c87e1be.
Since your change was applied there have been 110 commits pushed to the master branch:

7d1fe0e: 8339543: [vectorapi] laneHelper and withLaneHelper should be ForceInline
ddc4318: 8352628: Refine Grapheme test
d8c2f59: 8352064: AIX: now also able to build static-jdk image with a statically linked launcher
5709f79: 8352648: JFR: 'jfr query' should not be available in product builds
02a4ce2: 8352147: G1: TestEagerReclaimHumongousRegionsClearMarkBits test takes very long
de58009: 8351468: C2: array fill optimization assigns wrong type to intrinsic call
a875733: 8352486: [ubsan] compilationMemoryStatistic.cpp:659:21: runtime error: index 64 out of bounds for type const struct unnamed struct
5591f8a: 8351515: C2 incorrectly removes double negation for double and float
56a4ffa: 8352597: [IR Framework] test bug: TestNotCompilable.java fails on product build
e23e0f8: 8352591: Missing UnlockDiagnosticVMOptions in VerifyGraphEdgesWithDeadCodeCheckFromSafepoints test
... and 100 more: https://git.openjdk.org/jdk/compare/37ec796255ae857588a5c7e0d572407dd81cbec9...master

Your commit was automatically rebased without conflicts.

openjdk · 2025-03-24T16:44:36Z

@sviswa7 @vamsi-parasa Pushed as commit c87e1be.

💡 You may see a message that your pull request was closed with unmerged commits. This can be safely ignored.

TobiHartmann · 2025-05-06T15:32:18Z

This caused a regression: JDK-8356281 @vamsi-parasa Could you please have a look?

vamsi-parasa · 2025-05-06T15:38:07Z

This caused a regression: JDK-8356281 @vamsi-parasa Could you please have a look?

Hi Tobias, thank you for letting us know. I have been working on a fix for this issue over the last few days. The root cause has been figured out and it will be addressed soon.

8349582: APX NDD code generation for OpenJDK

e979438

openjdk bot added the rfr Pull request is ready for review label Feb 6, 2025

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vamsi-parasa mentioned this pull request Feb 6, 2025

APX NDD instruction support for OpenJDK #21941

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jatin-bhateja reviewed Feb 7, 2025

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revert to nf version for {pop/tz/lz}cnt count instructions

5306c39

sviswa7 reviewed Mar 5, 2025

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remove epopcount, elzcnt, etzcnt

f09266d

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add flag(PD::...) and clean up loadNKlassCompactHeaders

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vamsi-parasa added 9 commits March 6, 2025 11:11

Reorder to dst, src for negI and negL instructions

b09f1a0

remove APX support when bmi2 support is absent

be13918

ndd version of cmov eq/ne

630acb8

remove unused expand blocks;ndd version of orL_rReg_castP2X

e02ff23

Update copyright; remove extra lines

cb21e92

Remove randomly generated test_reg2 for dst= rax test

6343b76

restore eorl for RIR

cced83e

undo BoxLock node fix

126dd77

undo changes to testing implementation

51d0e0d

sviswa7 approved these changes Mar 12, 2025

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eme64 reviewed Mar 13, 2025

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eme64 reviewed Mar 24, 2025

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eme64 approved these changes Mar 24, 2025

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Update copyright for x86-asmtest.py

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openjdk bot removed the ready Pull request is ready to be integrated label Mar 24, 2025

eme64 reviewed Mar 24, 2025

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test/hotspot/gtest/x86/x86-asmtest.py Outdated Show resolved Hide resolved

Update copyright years in test/hotspot/gtest/x86/x86-asmtest.py

06c52ce

Co-authored-by: Emanuel Peter <emanuel.peter@oracle.com>

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vamsi-parasa mentioned this pull request Apr 14, 2025

8354544: Fix bugs in increment and xor APX codegen #24637

Closed

3 tasks

		%}


		instruct cmovI_regUCF2_ne(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegI dst, rRegI src) %{

8349582: APX NDD code generation for OpenJDK #23501

8349582: APX NDD code generation for OpenJDK #23501

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