Skip to content

8350940: RISC-V: remove unnecessary assert_different_registers in minmax_fp #23842

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Closed
Hamlin-Li wants to merge 4 commits into from
Closed

8350940: RISC-V: remove unnecessary assert_different_registers in minmax_fp #23842

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
4 commits
Select commit Hold shift + click to select a range
1aa9d89
initial commit
Feb 28, 2025
e910c62
merge master
Feb 28, 2025
f6fba6b
remove unnecessary effect
Feb 28, 2025
a5d9782
keep cr/t1 in effect
Feb 28, 2025
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
3 changes: 0 additions & 3 deletions src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -2135,9 +2135,6 @@ void C2_MacroAssembler::enc_cmove(int cmpFlag, Register op1, Register op2, Regis
// Set dst to NaN if any NaN input.
void C2_MacroAssembler::minmax_fp(FloatRegister dst, FloatRegister src1, FloatRegister src2,
bool is_double, bool is_min) {
assert_different_registers(dst, src1);
assert_different_registers(dst, src2);

Label Done, Compare;

is_double ? fclass_d(t0, src1)
Expand Down
8 changes: 4 additions & 4 deletions src/hotspot/cpu/riscv/riscv.ad
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -7287,7 +7287,7 @@ instruct nmaddD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{
// Math.max(FF)F
instruct maxF_reg_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr) %{
match(Set dst (MaxF src1 src2));
effect(TEMP_DEF dst, KILL cr);
effect(KILL cr);

format %{ "maxF $dst, $src1, $src2" %}

Expand All @@ -7303,7 +7303,7 @@ instruct maxF_reg_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr) %{
// Math.min(FF)F
instruct minF_reg_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr) %{
match(Set dst (MinF src1 src2));
effect(TEMP_DEF dst, KILL cr);
effect(KILL cr);

format %{ "minF $dst, $src1, $src2" %}

Expand All @@ -7319,7 +7319,7 @@ instruct minF_reg_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr) %{
// Math.max(DD)D
instruct maxD_reg_reg(fRegD dst, fRegD src1, fRegD src2, rFlagsReg cr) %{
match(Set dst (MaxD src1 src2));
effect(TEMP_DEF dst, KILL cr);
effect(KILL cr);

format %{ "maxD $dst, $src1, $src2" %}

Expand All @@ -7335,7 +7335,7 @@ instruct maxD_reg_reg(fRegD dst, fRegD src1, fRegD src2, rFlagsReg cr) %{
// Math.min(DD)D
instruct minD_reg_reg(fRegD dst, fRegD src1, fRegD src2, rFlagsReg cr) %{
match(Set dst (MinD src1 src2));
effect(TEMP_DEF dst, KILL cr);
effect(KILL cr);

format %{ "minD $dst, $src1, $src2" %}

Expand Down