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[Intel-SIG] Intel new platform ClearWater Forest support including CPU model/new ISAs and its dependency #71

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[Intel-SIG] Intel new platform ClearWater Forest support including CPU model/new ISAs and its dependency #71

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ce59662
KVM: x86: Advertise AVX-VNNI-INT8 CPUID to user space
Nov 25, 2022
0f64779
x86/cpu: Add model number for Intel Clearwater Forest processor
aegl Jan 17, 2024
eeb8a6b
x86: KVM: Advertise CPUIDs for new instructions in Clearwater Forest
taosu-linux Nov 5, 2024
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3 changes: 3 additions & 0 deletions arch/x86/include/asm/cpufeatures.h
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Original file line number Diff line number Diff line change
Expand Up @@ -317,6 +317,9 @@
#define X86_FEATURE_ZEN1 (11*32+31) /* "" CPU based on Zen1 microarchitecture */

/* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
#define X86_FEATURE_SHA512 (12*32+ 0) /* SHA512 instructions */
#define X86_FEATURE_SM3 (12*32+ 1) /* SM3 instructions */
#define X86_FEATURE_SM4 (12*32+ 2) /* SM4 instructions */
#define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */
#define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* AVX512 BFLOAT16 instructions */
#define X86_FEATURE_ARCH_PERFMON_EXT (12*32+ 8) /* "" Intel Architectural PerfMon Extension */
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7 changes: 5 additions & 2 deletions arch/x86/include/asm/intel-family.h
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Original file line number Diff line number Diff line change
Expand Up @@ -152,8 +152,11 @@
#define INTEL_FAM6_ATOM_TREMONT_L 0x9C /* Jasper Lake */

#define INTEL_FAM6_ATOM_GRACEMONT 0xBE /* Alderlake N */
#define INTEL_FAM6_ATOM_CRESTMONT_X 0xAF /* Sierra Forest */
#define INTEL_FAM6_ATOM_CRESTMONT 0xB6 /* Grand Ridge */
#define INTEL_FAM6_ATOM_CRESTMONT_X 0xAF /* Sierra Forest */
#define INTEL_FAM6_ATOM_CRESTMONT 0xB6 /* Grand Ridge */

#define INTEL_FAM6_ATOM_DARKMONT_X 0xDD /* Clearwater Forest */

/* Xeon Phi */

#define INTEL_FAM6_XEON_PHI_KNL 0x57 /* Knights Landing */
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8 changes: 6 additions & 2 deletions arch/x86/kvm/cpuid.c
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Original file line number Diff line number Diff line change
Expand Up @@ -524,10 +524,14 @@ void kvm_set_cpu_caps(void)
kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL_SSBD);

kvm_cpu_cap_mask(CPUID_7_1_EAX,
F(AVX_VNNI) | F(AVX512_BF16) |
F(SHA512) | F(SM3) | F(SM4) | F(AVX_VNNI) | F(AVX512_BF16) |
F(FZRM) | F(FSRS) | F(FSRC)
);

kvm_cpu_cap_init_scattered(CPUID_7_1_EDX,
F(AVX_VNNI_INT8) | F(AVX_VNNI_INT16)
);

kvm_cpu_cap_mask(CPUID_D_1_EAX,
F(XSAVEOPT) | F(XSAVEC) | F(XGETBV1) | F(XSAVES) | f_xfd
);
Expand Down Expand Up @@ -783,9 +787,9 @@ static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function)
goto out;

cpuid_entry_override(entry, CPUID_7_1_EAX);
cpuid_entry_override(entry, CPUID_7_1_EDX);
entry->ebx = 0;
entry->ecx = 0;
entry->edx = 0;
}
break;
case 0xa: { /* Architectural Performance Monitoring */
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6 changes: 6 additions & 0 deletions arch/x86/kvm/reverse_cpuid.h
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Original file line number Diff line number Diff line change
Expand Up @@ -13,6 +13,7 @@
*/
enum kvm_only_cpuid_leafs {
CPUID_12_EAX = NCAPINTS,
CPUID_7_1_EDX,
NR_KVM_CPU_CAPS,

NKVMCAPINTS = NR_KVM_CPU_CAPS - NCAPINTS,
Expand All @@ -24,6 +25,10 @@ enum kvm_only_cpuid_leafs {
#define KVM_X86_FEATURE_SGX1 KVM_X86_FEATURE(CPUID_12_EAX, 0)
#define KVM_X86_FEATURE_SGX2 KVM_X86_FEATURE(CPUID_12_EAX, 1)

/* Intel-defined sub-features, CPUID level 0x00000007:1 (EDX) */
#define X86_FEATURE_AVX_VNNI_INT8 KVM_X86_FEATURE(CPUID_7_1_EDX, 4)
#define X86_FEATURE_AVX_VNNI_INT16 KVM_X86_FEATURE(CPUID_7_1_EDX, 10)

struct cpuid_reg {
u32 function;
u32 index;
Expand All @@ -49,6 +54,7 @@ static const struct cpuid_reg reverse_cpuid[] = {
[CPUID_12_EAX] = {0x00000012, 0, CPUID_EAX},
[CPUID_8000_001F_EAX] = {0x8000001f, 0, CPUID_EAX},
[CPUID_8000_0021_EAX] = {0x80000021, 0, CPUID_EAX},
[CPUID_7_1_EDX] = { 7, 1, CPUID_EDX},
};

/*
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