Intel-SIG: new Intel X86 CPU model definition #72
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commit 24d74b9 upstream. AVX-VNNI-INT8 is a new set of instructions in the latest Intel platform Sierra Forest, aims for the platform to have superior AI capabilities. This instruction multiplies the individual bytes of two unsigned or unsigned source operands, then adds and accumulates the results into the destination dword element size operand. The bit definition: CPUID.(EAX=7,ECX=1):EDX[bit 4] AVX-VNNI-INT8 is on a new and sparse CPUID leaf and all bits on this leaf have no truly kernel use case for now. Given that and to save space for kernel feature bits, move this new leaf to KVM-only subleaf and plus an x86_FEATURE definition for AVX-VNNI-INT8 to direct it to the KVM entry. Advertise AVX-VNNI-INT8 to KVM userspace. This is safe because there are no new VMX controls or additional host enabling required for guests to use this feature. Intel-SIG: commit 24d74b9 KVM: x86: Advertise AVX-VNNI-INT8 CPUID to user space. ClearWater support including CPU model and new ISAs and its dependency Signed-off-by: Jiaxi Chen <jiaxi.chen@linux.intel.com> Message-Id: <20221125125845.1182922-7-jiaxi.chen@linux.intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <quanxian.wang@intel.com>
commit 090e3be upstream. Server product based on the Atom Darkmont core. Intel-SIG: commit 090e3be x86/cpu: Add model number for Intel Clearwater Forest processor. ClearWater support including CPU model and new ISAs and its dependency Signed-off-by: Tony Luck <tony.luck@intel.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Link: https://lore.kernel.org/r/20240117191844.56180-1-tony.luck@intel.com [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <quanxian.wang@intel.com>
commit a0423af92cb31e6fc4f53ef9b6e19fdf08ad4395 upstream. Latest Intel platform Clearwater Forest has introduced new instructions enumerated by CPUIDs of SHA512, SM3, SM4 and AVX-VNNI-INT16. Advertise these CPUIDs to userspace so that guests can query them directly. SHA512, SM3 and SM4 are on an expected-dense CPUID leaf and some other bits on this leaf have kernel usages. Considering they have not truly kernel usages, hide them in /proc/cpuinfo. These new instructions only operate in xmm, ymm registers and have no new VMX controls, so there is no additional host enabling required for guests to use these instructions, i.e. advertising these CPUIDs to userspace is safe. Intel-SIG: commit a0423af92cb3 x86: KVM: Advertise CPUIDs for new instructions in Clearwater Forest. ClearWater support including CPU model and new ISAs and its dependency Tested-by: Jiaan Lu <jiaan.lu@intel.com> Tested-by: Xuelian Guo <xuelian.guo@intel.com> Signed-off-by: Tao Su <tao1.su@linux.intel.com> Message-ID: <20241105054825.870939-1-tao1.su@linux.intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <quanxian.wang@intel.com>
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commit 8a8a9c9 upstream. This one is the regular laptop CPU. Intel-SIG: commit 8a8a9c9 x86/cpu: Add model number for another Intel Arrow Lake mobile processor. New Intel X86 CPU Family definition Signed-off-by: Tony Luck <tony.luck@intel.com> Signed-off-by: Ingo Molnar <mingo@kernel.org> Link: https://lore.kernel.org/r/20240322161725.195614-1-tony.luck@intel.com [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <quanxian.wang@intel.com>
commit a9d0adc upstream. Refactor struct cpuinfo_x86 so that the vendor, family, and model fields are overlaid in a union with a 32-bit field that combines all three (together with a one byte reserved field in the upper byte). This will make it easy, cheap, and reliable to check all three values at once. See https://lore.kernel.org/r/Zgr6kT8oULbnmEXx@agluck-desk3 for why the ordering is (low-to-high bits): (vendor, family, model) [ bp: Move comments over the line, add the backstory about the particular order of the fields. ] Intel-SIG: commit a9d0adc x86/cpu/vfm: Add/initialize x86_vfm field to struct cpuinfo_x86. New Intel X86 CPU Family definition Signed-off-by: Tony Luck <tony.luck@intel.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/r/20240416211941.9369-2-tony.luck@intel.com [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <quanxian.wang@intel.com>
commit e6dfdc2 upstream. To avoid adding a slew of new macros for each new Intel CPU family switch over from providing CPU model number #defines to a new scheme that encodes vendor, family, and model in a single number. [ bp: s/casted/cast/g ] Intel-SIG: commit e6dfdc2 x86/cpu/vfm: Add new macros to work with (vendor/family/model) values. New Intel X86 CPU Family definition Signed-off-by: Tony Luck <tony.luck@intel.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/r/20240416211941.9369-3-tony.luck@intel.com [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <quanxian.wang@intel.com>
This was referenced Oct 10, 2025
commit f055b62 upstream. New CPU #defines encode vendor and family as well as model. Update the example usage comment in arch/x86/kernel/cpu/match.c Intel-SIG: commit f055b62 x86/cpu/vfm: Update arch/x86/include/asm/intel-family.h. New Intel X86 CPU Family definition Signed-off-by: Tony Luck <tony.luck@intel.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/r/20240416211941.9369-4-tony.luck@intel.com [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <quanxian.wang@intel.com>
commit 744866f upstream. New CPU #defines encode vendor and family as well as model. Update INTEL_CPU_DESC() to work with vendor/family/model. Intel-SIG: commit 744866f x86/cpu: Switch to new Intel CPU model defines. New Intel X86 CPU Family definition Signed-off-by: Tony Luck <tony.luck@intel.com> Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com> Link: https://lore.kernel.org/all/20240520224620.9480-34-tony.luck%40intel.com [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <quanxian.wang@intel.com>
commit 6568fc1 upstream. New CPU #defines encode vendor and family as well as model. Intel-SIG: commit 6568fc1 x86/cpu/intel: Switch to new Intel CPU model defines. New Intel X86 CPU Family definition Signed-off-by: Tony Luck <tony.luck@intel.com> Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com> Link: https://lore.kernel.org/all/20240520224620.9480-29-tony.luck%40intel.com [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <quanxian.wang@intel.com>
commit 34b3fc5 upstream. The outer if () should have been dropped when switching to c->x86_vfm. Fixes: 6568fc1 ("x86/cpu/intel: Switch to new Intel CPU model defines") Intel-SIG: commit 34b3fc5 x86/cpu/intel: Drop stray FAM6 check with new Intel CPU model defines. New Intel X86 CPU Family definition Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Acked-by: Tony Luck <tony.luck@intel.com> Link: https://lore.kernel.org/r/20240529183605.17520-1-andrew.cooper3@citrix.com [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <quanxian.wang@intel.com>
commit d142df1 upstream. New CPU #defines encode vendor and family as well as model. Intel-SIG: commit d142df1 perf/x86/intel: Switch to new Intel CPU model defines. New Intel X86 CPU Family definition Signed-off-by: Tony Luck <tony.luck@intel.com> Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com> Link: https://lore.kernel.org/all/20240520224620.9480-32-tony.luck%40intel.com [ Quanxian Wang: amend commit log ] Signed-off-by: Quanxian Wang <quanxian.wang@intel.com>
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….15-velinux Note: this PR depends on openvelinux#71, openvelinux#72 is rebased on openvelinux#71 for testing. These patches series are to backport new Intel CPU family model definition (IFM), only on common parts and PMU special. Other modules will be update by domain owner when they use new definition. old/new definition co-exists at the same time. we will find a good chance to remove old definition when all are ready. there are 8 commits: Common(7): 34b3fc5,x86/cpu/intel: Drop stray FAM6 check with new Intel CPU model defines,2024-06-29 16:10:37,Andrew Cooper andrew.cooper3@citrix.com,v6.11-rc1 6568fc1,x86/cpu/intel: Switch to new Intel CPU model defines,2024-05-28 10:59:02,Tony Luck tony.luck@intel.com,v6.11-rc1 744866f,x86/cpu: Switch to new Intel CPU model defines,2024-05-28 10:59:03,Tony Luck tony.luck@intel.com,v6.11-rc1 f055b62,x86/cpu/vfm: Update arch/x86/include/asm/intel-family.h,2024-04-16 14:19:05,Tony Luck tony.luck@intel.com,v6.10-rc1 e6dfdc2,x86/cpu/vfm: Add new macros to work with (vendor/family/model) values,2024-04-16 14:19:04,Tony Luck tony.luck@intel.com,v6.10-rc1 a9d0adc,x86/cpu/vfm: Add/initialize x86_vfm field to struct cpuinfo_x86,2024-04-16 14:19:03,Tony Luck tony.luck@intel.com,v6.10-rc1 8a8a9c9,x86/cpu: Add model number for another Intel Arrow Lake mobile processor,2024-03-24 04:08:10,Tony Luck tony.luck@intel.com,v6.9-rc1 PMU special (1) d142df1,perf/x86/intel: Switch to new Intel CPU model defines,2024-05-28 10:59:02,Tony Luck tony.luck@intel.com,v6.11-rc1 Testing: Build / Boot PASS on CWF platform
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…5-velinux Support OOB CPU frequency control for EMR/GNR/SRF/GRR/CWF Test: This PR only takes effect on special SKUs with OOB cpu frequency control. Tested on regular GNR/CWF SKUs, no regression found. Note: This PR depends on the CWF CPUID support, so it is rebased on top of openvelinux#72 The first 11 patches are from openvelinux#72 1: KVM: x86: Advertise AVX-VNNI-INT8 CPUID to user space 2: x86/cpu: Add model number for Intel Clearwater Forest processor 3: x86: KVM: Advertise CPUIDs for new instructions in Clearwater Forest 4: x86/cpu: Add model number for another Intel Arrow Lake mobile processor 5: x86/cpu/vfm: Add/initialize x86_vfm field to struct cpuinfo_x86 6: x86/cpu/vfm: Add new macros to work with (vendor/family/model) values 7: x86/cpu/vfm: Update arch/x86/include/asm/intel-family.h 8: x86/cpu: Switch to new Intel CPU model defines 9: x86/cpu/intel: Switch to new Intel CPU model defines 10: x86/cpu/intel: Drop stray FAM6 check with new Intel CPU model defines 11: perf/x86/intel: Switch to new Intel CPU model defines 12: cpufreq: intel_pstate: Support Clearwater Forest OOB mode 13: cpufreq: intel_pstate: Support Granite Rapids and Sierra Forest OOB mode 14: cpufreq: intel_pstate: Support Emerald Rapids OOB mode
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…elinux Add SST support for ClearWater Forest Test: Tested on CWF, after the PR, the TPMI RAPL driver probe the TPMI RAPL devices, userspace intel-speed-select tool can show proper sst information. Note: This PR depends on the CWF CPUID support, so it is rebased on top of openvelinux#72 The first 11 patches are from openvelinux#72 1: KVM: x86: Advertise AVX-VNNI-INT8 CPUID to user space 2: x86/cpu: Add model number for Intel Clearwater Forest processor 3: x86: KVM: Advertise CPUIDs for new instructions in Clearwater Forest 4: x86/cpu: Add model number for another Intel Arrow Lake mobile processor 5: x86/cpu/vfm: Add/initialize x86_vfm field to struct cpuinfo_x86 6: x86/cpu/vfm: Add new macros to work with (vendor/family/model) values 7: x86/cpu/vfm: Update arch/x86/include/asm/intel-family.h 8: x86/cpu: Switch to new Intel CPU model defines 9: x86/cpu/intel: Switch to new Intel CPU model defines 10: x86/cpu/intel: Drop stray FAM6 check with new Intel CPU model defines 11: perf/x86/intel: Switch to new Intel CPU model defines 12: platform/x86: ISST: Add Clearwater Forest to support list
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…elinux Add IFS support for ClearWater Forest Test: Tested on CWF platform, IFS test cases passed. Note: This PR depends on the CWF CPUID support, so it is rebased on top of openvelinux#72 The first 11 patches are from openvelinux#72 1: KVM: x86: Advertise AVX-VNNI-INT8 CPUID to user space 2: x86/cpu: Add model number for Intel Clearwater Forest processor 3: x86: KVM: Advertise CPUIDs for new instructions in Clearwater Forest 4: x86/cpu: Add model number for another Intel Arrow Lake mobile processor 5: x86/cpu/vfm: Add/initialize x86_vfm field to struct cpuinfo_x86 6: x86/cpu/vfm: Add new macros to work with (vendor/family/model) values 7: x86/cpu/vfm: Update arch/x86/include/asm/intel-family.h 8: x86/cpu: Switch to new Intel CPU model defines 9: x86/cpu/intel: Switch to new Intel CPU model defines 10: x86/cpu/intel: Drop stray FAM6 check with new Intel CPU model defines 11: perf/x86/intel: Switch to new Intel CPU model defines 12: platform/x86/intel/ifs: Add Clearwater Forest to CPU support list
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…velinux Add EDAC basic support and RRL enhancement for CWF/SRF/GNR/GNR-D Tests: Tested on GNR, the error injection works as expected, the Machine check exceptions are dumped with extra RRL information. Tested on GNR-D/CWF, the EDAC/Error injection starts to work. the Machine check exceptions are dumped together with RRL information. Note: This PR depends on the CWF CPUID support, so it is rebased on top of openvelinux#72 The first 11 patches are from openvelinux#72 1: KVM: x86: Advertise AVX-VNNI-INT8 CPUID to user space 2: x86/cpu: Add model number for Intel Clearwater Forest processor 3: x86: KVM: Advertise CPUIDs for new instructions in Clearwater Forest 4: x86/cpu: Add model number for another Intel Arrow Lake mobile processor 5: x86/cpu/vfm: Add/initialize x86_vfm field to struct cpuinfo_x86 6: x86/cpu/vfm: Add new macros to work with (vendor/family/model) values 7: x86/cpu/vfm: Update arch/x86/include/asm/intel-family.h 8: x86/cpu: Switch to new Intel CPU model defines 9: x86/cpu/intel: Switch to new Intel CPU model defines 10: x86/cpu/intel: Drop stray FAM6 check with new Intel CPU model defines 11: perf/x86/intel: Switch to new Intel CPU model defines 12: memblock: use numa_valid_node() helper to check for invalid node ID 13: EDAC/i10nm: Add Intel Grand Ridge micro-server support 14: EDAC/{skx_common,i10nm}: Fix some missing error reports on Emerald Rapids 15: EDAC/{skx_common,i10nm}: Fix the loss of saved RRL for HBM pseudo channel 0 16: EDAC/{skx_common,i10nm}: Remove the AMAP register for determing DDR5 17: EDAC/i10nm: Add Intel Clearwater Forest server support 18: EDAC/{i10nm,skx,skx_common}: Support UV systems 19: EDAC/i10nm: Explicitly set the modes of the RRL register sets 20: EDAC/{skx_common,i10nm}: Structure the per-channel RRL registers 21: EDAC/{skx_common,i10nm}: Refactor enable_retry_rd_err_log() 22: EDAC/{skx_common,i10nm}: Refactor show_retry_rd_err_log() 23: EDAC/{skx_common,i10nm}: Add RRL support for Intel Granite Rapids server 24: EDAC/i10nm: Fix the bitwise operation between variables of different sizes 25: EDAC/i10nm: Add Intel Granite Rapids-D support 26: EDAC/{skx_common,i10nm}: Use scnprintf() for safer buffer handling
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…velinux Support intel_idle for GNR-D/CWF for 5.15 Tests: Tested on GNR-D/CWF, intel_idle driver can be loaded with cstates from custom table. Note: This PR depends on the CWF CPUID support, so it is rebased on top of openvelinux#72 The first 11 patches are from openvelinux#72 1: KVM: x86: Advertise AVX-VNNI-INT8 CPUID to user space 2: x86/cpu: Add model number for Intel Clearwater Forest processor 3: x86: KVM: Advertise CPUIDs for new instructions in Clearwater Forest 4: x86/cpu: Add model number for another Intel Arrow Lake mobile processor 5: x86/cpu/vfm: Add/initialize x86_vfm field to struct cpuinfo_x86 6: x86/cpu/vfm: Add new macros to work with (vendor/family/model) values 7: x86/cpu/vfm: Update arch/x86/include/asm/intel-family.h 8: x86/cpu: Switch to new Intel CPU model defines 9: x86/cpu/intel: Switch to new Intel CPU model defines 10: x86/cpu/intel: Drop stray FAM6 check with new Intel CPU model defines 11: perf/x86/intel: Switch to new Intel CPU model defines 12: intel_idle: add Granite Rapids Xeon D support 13: intel_idle: add Clearwater Forest SoC support
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Note:
this PR depends on #71, #72 is rebased on #71 for testing.
These patches series are to backport new Intel CPU family model definition (IFM), only on common parts and PMU special.
Other modules will be update by domain owner when they use new definition.
old/new definition co-exists at the same time. we will find a good chance to remove old definition when all are ready.
there are 8 commits:
Common(7):
34b3fc5,x86/cpu/intel: Drop stray FAM6 check with new Intel CPU model defines,2024-06-29 16:10:37,Andrew Cooper andrew.cooper3@citrix.com,v6.11-rc1
6568fc1,x86/cpu/intel: Switch to new Intel CPU model defines,2024-05-28 10:59:02,Tony Luck tony.luck@intel.com,v6.11-rc1
744866f,x86/cpu: Switch to new Intel CPU model defines,2024-05-28 10:59:03,Tony Luck tony.luck@intel.com,v6.11-rc1
f055b62,x86/cpu/vfm: Update arch/x86/include/asm/intel-family.h,2024-04-16 14:19:05,Tony Luck tony.luck@intel.com,v6.10-rc1
e6dfdc2,x86/cpu/vfm: Add new macros to work with (vendor/family/model) values,2024-04-16 14:19:04,Tony Luck tony.luck@intel.com,v6.10-rc1
a9d0adc,x86/cpu/vfm: Add/initialize x86_vfm field to struct cpuinfo_x86,2024-04-16 14:19:03,Tony Luck tony.luck@intel.com,v6.10-rc1
8a8a9c9,x86/cpu: Add model number for another Intel Arrow Lake mobile processor,2024-03-24 04:08:10,Tony Luck tony.luck@intel.com,v6.9-rc1
PMU special (1)
d142df1,perf/x86/intel: Switch to new Intel CPU model defines,2024-05-28 10:59:02,Tony Luck tony.luck@intel.com,v6.11-rc1
Testing: Build / Boot PASS on CWF platform