fix(v2.1): change block size in ecc chips to 4

[shuklaayush]

Summary

Adapt projective EC extension to v2's DEFAULT_BLOCK_SIZE=4 memory constraint.

The projective coordinates code used BLOCK_SIZE=32 (secp256k1) and BLOCK_SIZE=16 (BLS12-381) for memory accesses, but v2's TracingMemory enforces 4-cell accesses. This updates:

• ECC_BLOCKS constants from 2 * NUM_LIMBS / 4 (affine, 2 coords) to 3 * NUM_LIMBS / 4 (projective, 3 coords)
• All hardcoded <3, 32> / <9, 16> const generics to <ECC_BLOCKS_N, DEFAULT_BLOCK_SIZE> in extension, hybrid, and test code
• Test helpers to write memory in 4-byte chunks

resolves int-6644

[github-actions]

Claude finished @shuklaayush's task in 1m 15s —— View job

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Overview

The PR correctly adapts the projective ECC extension to v2's DEFAULT_BLOCK_SIZE=4 memory constraint. The change is mechanical but consistent across all code paths.

Verification

Constants (lib.rs):

• ECC_BLOCKS_32 = 3 * (32 / 4) = 24 — correct for 3 projective coordinates (X, Y, Z) × 8 blocks each
• ECC_BLOCKS_48 = 3 * (48 / 4) = 36 — correct for 3 projective coordinates × 12 blocks each

All call sites updated consistently:

• WeierstrassExtensionExecutor enum — variants use ECC_BLOCKS_* / DEFAULT_BLOCK_SIZE ✓
• VmCircuitExtension impl (weierstrass.rs) — get_ec_add_air and get_ec_double_air ✓
• EccCpuProverExt impl (weierstrass.rs) — WeierstrassAir, get_ec_add_chip, get_ec_double_chip ✓
• HybridProverExt impl (hybrid.rs) — same treatment ✓
• Tests — all run_ec_add_test, run_ec_double_test, CUDA tests, and step tests updated ✓

No remaining hardcoded <3, 32> or <9, 16> values in extensions/ecc/circuit/src/.

CUDA router (rv32_vec_heap_router.cuh):

• adapter_blocks == 24 correctly nested inside num_limbs <= 32 (32-limb curves)
• adapter_blocks == 36 correctly at the outer level (48-limb curves, num_limbs > 32)
• num_inputs == 3 → 1 read (ec_double: 1 projective point), else → 2 reads (ec_add: 2 projective points) — consistent with existing affine pattern (num_inputs == 2 → 1 read)
• All 4 template instantiations in route_rv32_vec_heap_adapter match the config cases ✓

Ancillary changes:

• Nextest config adds serial execution for CUDA ECC tests (GPU OOM prevention) — sensible
• k256/p256 test imports updated for renamed CUDA engine types — unrelated fixup, correct

Verdict

LGTM. The fix is complete, consistent, and well-scoped. No issues found.

[github-actions]

group	app.proof_time_ms	app.cycles	leaf.proof_time_ms
fibonacci	3,835	12,000,265	945
keccak	18,474	18,655,329	3,294
regex	1,421	4,137,067	369
ecrecover	733	317,792	353
pairing	910	1,745,757	312
kitchen_sink	2,545	2,580,026	548

Note: cells_used metrics omitted because CUDA tracegen does not expose unpadded trace heights.

Commit: c03ed4d

Benchmark Workflow

[Tuanlinh12312]

LGTM aside from the two naming cleanups!