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kernel: rtl8261n: Always configure as USXGMII#23076

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openwrt-bot merged 3 commits intoopenwrt:mainfrom
ecsv:rtl8261n-std-usxgmii
Apr 25, 2026
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kernel: rtl8261n: Always configure as USXGMII#23076
openwrt-bot merged 3 commits intoopenwrt:mainfrom
ecsv:rtl8261n-std-usxgmii

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@ecsv ecsv commented Apr 24, 2026

In the past, all the configuration of SerDes and PHYs on the realtek switches were done using u-boot (rtk init). But since RTL930x switched to SerDes configuration under Linux, the SoC side is no longer using the Realtek-proprietary variant of USXGMII. The communication to the RTL8261N PHYs on those switches broke because of this incompatibility.

Enabling the full initialization on CONFIG_MACH_REALTEK_RTL converts also the PHY side to the standard USXGMII and therefore ensures that both sides speak the same dialect.

In this process, also an undocumented CONFIG_MACH_REALTEK_RTL only patch needs to be removed. It was never actually reached before. Simply, because rtkphy_config_init() returned on CONFIG_MACH_REALTEK_RTL switches before the PHY patching was reached. But it also seems to be wrong to apply it now. The SerDes<->PHY communication should use the standard USXGMII and not some proprietary Realtek variant.


This was mostly extracted from a discussion with @jonasjelonek (#22563 (comment))

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ecsv commented Apr 24, 2026

@jonasjelonek Can you please double check this PR? Not that I've messed something up. You have much more knowledge in this field.

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Let's see how many additional IRQ comments it'll take until the other PR is in so the old driver can be dropped ...

Otherwise good, also just tested this on my Realtek switch with RTL8261 and it works.

Comment thread target/linux/generic/files/drivers/net/phy/rtl8261n/rtk_phy.c
@github-actions github-actions Bot added the kernel pull request/issue with Linux kernel related changes label Apr 24, 2026
@ecsv ecsv force-pushed the rtl8261n-std-usxgmii branch from f9cdf08 to 27bddb2 Compare April 24, 2026 09:15
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Thank you. Tested on (yet unsupported) SKS7300-4X4T with RTL8261N

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Please reword the first commit message. Some clumsy sentences there.

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And another nit. In the last commit ther is a ":" missing

Signed-off-by Jonas Jelonek <jelonek.jonas@gmail.com>

@ecsv ecsv force-pushed the rtl8261n-std-usxgmii branch 5 times, most recently from 11e3b02 to 282c30d Compare April 24, 2026 11:53
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ecsv commented Apr 24, 2026

Please reword the first commit message. Some clumsy sentences there.

Reworded it - will stop for now because I think I've ended up in a loop of rewording-only pushes.

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@robimarko good to go. Thanks in advance.

ecsv and others added 3 commits April 25, 2026 19:56
The PHY register patch in question is gated by `CONFIG_MACH_REALTEK_RTL`,
has no documented/expected behavior, and is in practice unreachable:
`phy_patch()` is only called from `rtkphy_config_init()`, which is exits
(too) early for `CONFIG_MACH_REALTEK_RTL` builds.

Remove it as a cleanup step before enabling standard USXGMII configuration
for these PHYs.

Fixes: b77fa45 ("kernel: fix rtl8261n driver for realtek")
Co-authored-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Signed-off-by: Sven Eckelmann <sven@narfation.org>
Link: openwrt#23076
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
In the past, all the configuration of SerDes and PHYs on the realtek
switches were done  using u-boot (`rtk init`). But since RTL930x switched
to SerDes configuration under Linux, the SoC side is no longer using the
Realtek-proprietary variant of USXGMII. The communication to the RTL8261N
PHYs on those switches broke because of this incompatibility.

Enabling the full initialization on `CONFIG_MACH_REALTEK_RTL` converts also
the PHY side to the standard USXGMII and therefore ensures that both sides
speak the same dialect.

Co-authored-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Signed-off-by: Sven Eckelmann <sven@narfation.org>
Link: openwrt#23076
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
After the RTL8261N asserts a reset, the MDIO bus becomes temporarily
unavailable during the chip's reinitialization sequence. Any subsequent
read or write issued before the PHY has stabilized will fail.

Add a 30ms delay after triggering the reset to ensure the chip is reachable
via MDIO before resuming communication.

Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Signed-off-by: Sven Eckelmann <sven@narfation.org>
Link: openwrt#23076
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
@hauke hauke force-pushed the rtl8261n-std-usxgmii branch from 282c30d to 51992c8 Compare April 25, 2026 17:57
@openwrt-bot openwrt-bot merged commit 51992c8 into openwrt:main Apr 25, 2026
5 checks passed
@ecsv ecsv deleted the rtl8261n-std-usxgmii branch April 25, 2026 17:58
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4 participants