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Unfortunately there are not too many good options aside from simply avoiding namespace conflicts directly. This is an issue with Verilog/SystemVerilog as well, and often the solution is to simply modify component names with an org/project prefix. I have been advocating for C++-style namespaces in Verilog for a while, and would definitely support such a feature in SystemRDL. I would recommend reaching out to (and putting pressure on) Accellera, as they are the governing organization for the SystemRDL language. Increasingly I believe that there needs to be an effort to continue development of the SystemRDL language, and convincing Accellera of that fact is the first step. |
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When integrating multiple IPs we often encounter subsystems that instantiate RDL files or addressmaps sharing the exact same name but containing different content.
The RDL syntax doesn't have a namespace identifier like other langaugues, how do you suggest avoiding name collisions in multi IP enviorments?
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