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    • verilator

      Public
      Verilator open-source SystemVerilog simulator and lint system
      C++
      GNU Lesser General Public License v3.0
      771000Updated May 29, 2024May 29, 2024
    • minisat

      Public
      A minimalistic and high-performance SAT solver
      C++
      Other
      412000Updated Mar 4, 2024Mar 4, 2024
    • apb_qemu

      Public
      D
      0000Updated Jun 29, 2023Jun 29, 2023
    • Example setup for UVM driven Icarus Verilog Simulation
      D
      35700Updated Jun 13, 2023Jun 13, 2023
    • avmm_sha3

      Public
      Verilog
      Other
      4100Updated Jan 24, 2022Jan 24, 2022
    • Tool to automate the generation of APB RTL file and RAL Model using given Register Specification sheet.
      D
      1000Updated Aug 15, 2021Aug 15, 2021
    • reg_debug

      Public
      An Open-Source Solution for Interactive Register Debugging using given Register Specification sheet for Register Verification
      Python
      1000Updated Aug 14, 2021Aug 14, 2021
    • UVM testbench for de10-nano CycloneV board
      D
      Other
      8200Updated Jan 23, 2021Jan 23, 2021
    • Verilog
      25213Updated Oct 20, 2019Oct 20, 2019
    • Verilog
      Other
      3500Updated Jun 21, 2019Jun 21, 2019
    • UVM Testbench for Keccak sha3 core downloaded from Opencores https://opencores.org/projects/sha3
      Verilog
      Other
      4500Updated Jun 15, 2019Jun 15, 2019