Adding new trigonometric instruction on RISC-V ISA to characterize and test an workload

[baul-iisc]

Hello team, I am looking for some help regarding adding new instruction on RISC-V ISA to characterize and test my workload. I was going through different source here and there how to add new instructions on gem5. I got from 2022 boot camp that, we need to add the instruction in the src/arch/riscv/isa/decoder.isa. But where to implement these micro-operation to carryout the execution? It will be really helpful if you please guide me some end to end process of additing new instruction on riscv isa to execute the workload.

[iagocaran]

Hi @baul-iisc,

I did something similar and can give you some ideas on how to proceed.

If you have a simpler instruction, you can use one of the templates that already exist and have the same operands as the instruction you want to add. I would recommend you to look at the files included by the src/arch/riscv/isa/formats/formats.isa.
Using one of those templates, you can add the the instruction to the src/arch/riscv/isa/decoder.isa and implement its functionality directly in it.
That may pollute a little the decoder.isa, so I would recommend you to create your own format file and include it like the others. In it, you can add your code directly and then start studying the .isa files and understanding how the ISA Parser generates the final code.
I would recommend you to look at the decoder-ns.hh.inc, decoder-ns.cc.inc and exec-ns.cc.inc files inside of build/RISCV/arch/riscv/generated/.

[baul-iisc]

Hello, Thank you for your suggestions , I am completely new to gem5, that’s why I am looking help. As I told earlier, I am able to add these custom instructions in gem5 decoder.isa file. But to execute my workloads using these custom instructions, what are all the steps need to be done? What are all the files need to add/modify? I have even generated all the .c and .h files for these trigonometric operations. Sent from Outlook for iOS<https://aka.ms/o0ukef>

…

________________________________ From: Iago Caran ***@***.***> Sent: Thursday, August 1, 2024 8:06:39 AM To: gem5/gem5 ***@***.***> Cc: Boul Chandra Garai ***@***.***>; Mention ***@***.***> Subject: Re: [gem5/gem5] Adding new trigonometric instruction on RISC-V ISA to characterize and test an workload (Discussion #1368) External Email Hi @baul-iisc<https://github.com/baul-iisc>, I did something similar and can give you some ideas on how to proceed. If you have a simpler instruction, you can use one of the templates that already exist and have the same operands as the instruction you want to add. I would recommend you to look at the files included by the src/arch/riscv/isa/formats/formats.isa. Using one of those templates, you can add the the instruction to the src/arch/riscv/isa/decoder.isa and implement its functionality directly in it. That may pollute a little the decoder.isa, so I would recommend you to create your own format file and include it like the others. In it, you can add your code directly and then start studying the .isa files and understanding how the ISA Parser generates the final code. I would recommend you to look at the decoder-ns.hh.inc, decoder-ns.cc.inc and exec-ns.cc.inc files inside of build/RISCV/arch/riscv/generated/. — Reply to this email directly, view it on GitHub<#1368 (comment)>, or unsubscribe<https://github.com/notifications/unsubscribe-auth/BF54XBF3IMH4ZHJQPVRBRLTZPGNLPAVCNFSM6AAAAABLIFICLGVHI2DSMVQWIX3LMV43URDJONRXK43TNFXW4Q3PNVWWK3TUHMYTAMRQG4YDMMY>. You are receiving this because you were mentioned.Message ID: ***@***.***>

[baul-iisc]

Hello, After adding these custom trigonometric instructions when I am rebuilding the gem5 getting the following errors, can you please help me to identify the issue, and how to correct the errors? "/data/home/chandraboul/development/gem5-riscv/gem5/build/RISCV/gem5py_m5" "build_tools/sim_object_param_struct_hh.py" "m5.objects.Process" "/data/home/chandraboul/development/gem5-riscv/gem5/build/RISCV/params/Process.hh" "/data/home/chandraboul/development/gem5-riscv/gem5/build/RISCV/gem5py_m5" "build_tools/sim_object_param_struct_cc.py" "m5.objects.BloomFilters" "/data/home/chandraboul/development/gem5-riscv/gem5/build/RISCV/python/_m5/param_BloomFilterBase.cc" "True" terminate called after throwing an instance of 'pybind11::error_already_set' what(): TypeError: Enum param got bad value 'SimdExt' (not in ['No_OpClass', 'IntAlu', 'IntMult', 'IntDiv', 'FloatAdd', 'FloatCmp', 'FloatCvt', 'FloatMult', 'FloatMultAcc', 'FloatDiv', 'FloatMisc', 'FloatSqrt', 'FloatSin', 'FloatCos', 'FloatTan', 'SimdAdd', 'SimdAddAcc', 'SimdAlu', 'SimdCmp', 'SimdCvt', 'SimdMisc', 'SimdMult', 'SimdMultAcc', 'SimdMatMultAcc', 'SimdShift', 'SimdShiftAcc', 'SimdDiv', 'SimdSqrt', 'SimdFloatAdd', 'SimdFloatAlu', 'SimdFloatCmp', 'SimdFloatCvt', 'SimdFloatDiv', 'SimdFloatMisc', 'SimdFloatMult', 'SimdFloatMultAcc', 'SimdFloatMatMultAcc', 'SimdFloatSqrt', 'SimdReduceAdd', 'SimdReduceAlu', 'SimdReduceCmp', 'SimdFloatReduceAdd', 'SimdFloatReduceCmp', 'SimdAes', 'SimdAesMix', 'SimdSha1Hash', 'SimdSha1Hash2', 'SimdSha256Hash', 'SimdSha256Hash2', 'SimdShaSigma2', 'SimdShaSigma3', 'SimdPredAlu', 'Matrix', 'MatrixMov', 'MatrixOP', 'MemRead', 'MemWrite', 'FloatMemRead', 'FloatMemWrite', 'IprAccess', 'InstPrefetch', 'VectorUnitStrideLoad', 'VectorUnitStrideStore', 'VectorUnitStrideMaskLoad', 'VectorUnitStrideMaskStore', 'VectorStridedLoad', 'VectorStridedStore', 'VectorIndexedLoad', 'VectorIndexedStore', 'VectorUnitStrideFaultOnlyFirstLoad', 'VectorWholeRegisterLoad', 'VectorWholeRegisterStore', 'VectorIntegerArith', 'VectorFloatArith', 'VectorFloatConvert', 'VectorIntegerReduce', 'VectorFloatReduce', 'VectorMisc', 'VectorIntegerExtension', 'VectorConfig']) Error setting param MinorOpClass.opClass to SimdExt At: src/python/m5/params.py(1603): __init__ src/python/m5/params.py(224): convert src/python/m5/SimObject.py(888): __setattr__ src/python/m5/SimObject.py(773): __init__ src/cpu/minor/BaseMinorCPU.py(119): boxOpClass src/cpu/minor/BaseMinorCPU.py(121): <listcomp> src/cpu/minor/BaseMinorCPU.py(121): minorMakeOpClassSet src/cpu/minor/BaseMinorCPU.py(173): MinorDefaultFloatSimdFU src/cpu/minor/BaseMinorCPU.py(172): <module> <string>(40): exec_module <frozen importlib._bootstrap>(703): _load_unlocked <frozen importlib._bootstrap>(1006): _find_and_load_unlocked <frozen importlib._bootstrap>(1027): _find_and_load <string>(1): <module> src/python/m5/objects/__init__.py(29): <module> <string>(40): exec_module <frozen importlib._bootstrap>(703): _load_unlocked <frozen importlib._bootstrap>(1006): _find_and_load_unlocked <frozen importlib._bootstrap>(1027): _find_and_load <frozen importlib._bootstrap>(1050): _gcd_import <frozen importlib._bootstrap>(241): _call_with_frames_removed <frozen importlib._bootstrap>(992): _find_and_load_unlocked <frozen importlib._bootstrap>(1027): _find_and_load <frozen importlib._bootstrap>(1050): _gcd_import /usr/lib/python3.10/importlib/__init__.py(126): import_module build_tools/sim_object_param_struct_cc.py(70): <module> terminate called after throwing an instance of 'pybind11::error_already_set' what(): TypeError: Enum param got bad value 'SimdExt' (not in ['No_OpClass', 'IntAlu', 'IntMult', 'IntDiv', 'FloatAdd', 'FloatCmp', 'FloatCvt', 'FloatMult', 'FloatMultAcc', 'FloatDiv', 'FloatMisc', 'FloatSqrt', 'FloatSin', 'FloatCos', 'FloatTan', 'SimdAdd', 'SimdAddAcc', 'SimdAlu', 'SimdCmp', 'SimdCvt', 'SimdMisc', 'SimdMult', 'SimdMultAcc', 'SimdMatMultAcc', 'SimdShift', 'SimdShiftAcc', 'SimdDiv', 'SimdSqrt', 'SimdFloatAdd', 'SimdFloatAlu', 'SimdFloatCmp', 'SimdFloatCvt', 'SimdFloatDiv', 'SimdFloatMisc', 'SimdFloatMult', 'SimdFloatMultAcc', 'SimdFloatMatMultAcc', 'SimdFloatSqrt', 'SimdReduceAdd', 'SimdReduceAlu', 'SimdReduceCmp', 'SimdFloatReduceAdd', 'SimdFloatReduceCmp', 'SimdAes', 'SimdAesMix', 'SimdSha1Hash', 'SimdSha1Hash2', 'SimdSha256Hash', 'SimdSha256Hash2', 'SimdShaSigma2', 'SimdShaSigma3', 'SimdPredAlu', 'Matrix', 'MatrixMov', 'MatrixOP', 'MemRead', 'MemWrite', 'FloatMemRead', 'FloatMemWrite', 'IprAccess', 'InstPrefetch', 'VectorUnitStrideLoad', 'VectorUnitStrideStore', 'VectorUnitStrideMaskLoad', 'VectorUnitStrideMaskStore', 'VectorStridedLoad', 'VectorStridedStore', 'VectorIndexedLoad', 'VectorIndexedStore', 'VectorUnitStrideFaultOnlyFirstLoad', 'VectorWholeRegisterLoad', 'VectorWholeRegisterStore', 'VectorIntegerArith', 'VectorFloatArith', 'VectorFloatConvert', 'VectorIntegerReduce', 'VectorFloatReduce', 'VectorMisc', 'VectorIntegerExtension', 'VectorConfig']) Error setting param MinorOpClass.opClass to SimdExt

…

________________________________ From: Boul Chandra Garai ***@***.***> Sent: Saturday, August 3, 2024 3:07 PM To: gem5/gem5 ***@***.***>; gem5/gem5 ***@***.***> Cc: Mention ***@***.***> Subject: Re: [gem5/gem5] Adding new trigonometric instruction on RISC-V ISA to characterize and test an workload (Discussion #1368) Hello, Thank you for your suggestions , I am completely new to gem5, that’s why I am looking help. As I told earlier, I am able to add these custom instructions in gem5 decoder.isa file. But to execute my workloads using these custom instructions, what are all the steps need to be done? What are all the files need to add/modify? I have even generated all the .c and .h files for these trigonometric operations. Sent from Outlook for iOS<https://aka.ms/o0ukef>

________________________________ From: Iago Caran ***@***.***> Sent: Thursday, August 1, 2024 8:06:39 AM To: gem5/gem5 ***@***.***> Cc: Boul Chandra Garai ***@***.***>; Mention ***@***.***> Subject: Re: [gem5/gem5] Adding new trigonometric instruction on RISC-V ISA to characterize and test an workload (Discussion #1368) External Email Hi @baul-iisc<https://github.com/baul-iisc>, I did something similar and can give you some ideas on how to proceed. If you have a simpler instruction, you can use one of the templates that already exist and have the same operands as the instruction you want to add. I would recommend you to look at the files included by the src/arch/riscv/isa/formats/formats.isa. Using one of those templates, you can add the the instruction to the src/arch/riscv/isa/decoder.isa and implement its functionality directly in it. That may pollute a little the decoder.isa, so I would recommend you to create your own format file and include it like the others. In it, you can add your code directly and then start studying the .isa files and understanding how the ISA Parser generates the final code. I would recommend you to look at the decoder-ns.hh.inc, decoder-ns.cc.inc and exec-ns.cc.inc files inside of build/RISCV/arch/riscv/generated/. — Reply to this email directly, view it on GitHub<#1368 (comment)>, or unsubscribe<https://github.com/notifications/unsubscribe-auth/BF54XBF3IMH4ZHJQPVRBRLTZPGNLPAVCNFSM6AAAAABLIFICLGVHI2DSMVQWIX3LMV43URDJONRXK43TNFXW4Q3PNVWWK3TUHMYTAMRQG4YDMMY>. You are receiving this because you were mentioned.Message ID: ***@***.***>