Gem5 support

[seaver-olson]

Hi all,

I’m an undergraduate working on extending gem5 with x86 VMX support (long-term goal: enabling hypervisor-style workloads / nested virtualization experiments).

I’ve been working mostly independently and have run into challenges around architectural decisions (e.g., VMCS modeling, VM-exit handling, and integration with the page table walker).

Are there any active community spaces outside GitHub Discussions where gem5 developers or researchers coordinate (Slack, Discord, mailing lists, etc.)?

Additionally, are there preferred channels for discussing deeper architectural questions related to gem5 internals?

Thanks—I’d appreciate any direction.

[Sir-NoChill]

There is an upcoming survey to see where people go to get help with gem5, ping the question again in a couple weeks and we might have some results but as far as I know this is the best forum for help. There is a slack, but it is largely inactive.

Your project seems cool, if you have any specific questions you want to discuss this forum is probably the best place to do so. In terms of virtualization, IIRC there are x86 ISA extensions that you need for VMX as well.

• You made me look up what the VMCS is, so thanks for the new knowledge. For this I would recommend trying to set up something similar to what gem5 currently does for multithreading context switches in full system mode. You probably want to model the VM state as a similar context-like environment in the register file and associated structures. I'm not familiar with the code for that, but if you have any specific questions then feel free to ping.
• Page Table Integration: My guess would be that this is associated with the VMCS, in that we will associate an extra bit in the TLB to the VMCS and then invalidate the TLB entries on context switch. You probably don't need to make any significant changes to the page table walkers themselves, but do correct me if my understanding is incorrect.
• VM Exit Handling: What do you mean? Are you talking specifically about some interrupt in x86 or something else?