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Updated for LCN disscussion and add a table for the tests used in my PoC branch. |
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Hi all,
I have been extending gem5's Ruby CHI model to support coherent chip-to-chip communication for chiplet-style systems. The current proof-of-concept branch is
dev_chi_c2c_poc. This is personal research work, not a corporate project.The main references are ARM IHI 0098 Issue A.b and Fabian Schätzle's CHI C2C work. The implementation is not intended to be a complete bit-accurate model of the full C2C stack yet. The goal is to add enough protocol structure to gem5's existing Ruby CHI model to study coherent multi-chip systems, directory behavior, traffic distribution, and inter-chip bottlenecks.
I would like feedback on whether this direction is useful for upstream gem5, what subset would be appropriate for review, and where maintainers would prefer the boundary between reusable simulator support and project-specific evaluation infrastructure.
Why this matters
For CHI-based systems, a chip boundary is more than an added latency term. Once coherent traffic leaves a chip, the model needs to answer questions such as:
gem5 already has a strong Ruby CHI foundation. Extending that foundation to multi-chip coherent systems would make it possible to study chiplet memory systems without replacing the coherence model with an abstract traffic-only approximation.
What exists in the code today
The implementation is centered on a separate
MachineType:CHI_C2CRuby controller rather than folding gateway behavior into an existing cache or home node. The controller has on-chip and C2C-side buffers for REQ, SNP, RSP, DAT, and MISC traffic.The gateway currently models:
DBIDRespandCompmay arrive in either order andCompDBIDResprepresents both,There is also an optional local
ReadSharedmerge optimization before traffic enters the C2C path. This is not a CHI C2C protocol feature; it is a Ruby-side gateway optimization that can coalesce compatible localReadSharedrequests behind one outbound C2C read and fan the completion back out locally.The code also carries the identity and directory state needed for gatewayed coherence:
(src, txnId, addr); inbound C2C matching is scoped by(peerGateway, txnId, addr); outbound C2C traffic uses gateway-assigned transaction IDs.SrcIDs can remain outstanding at the C2C gateway at the same time. The gateway uses transaction keys rather than an address-only TBE key, so one active line address does not serialize all independent requestors.CompAcks are still matched precisely.On the transport side, the branch includes
C2CPacketizerBridgeand Format X container/packetizer support. The bridge still forwards Ruby message objects, but packetization is active in the runtime path to model container occupancy, TX queue pressure, latency, and delayed credit return. A per-message-class C2C credit manager tracks REQ, SNP, RSP, and DAT credits and exposes related stats.Topology and configuration support includes two-chip and four-chip CHI C2C setups, R2/R3
ruby_mem_teststress configurations, SE workload configurations, and focused directed protocol-flow tests.Current scope and non-goals
This is a protocol-functional and timing-oriented CHI C2C model. It should be read as usable support for coherent multi-chip research in gem5, not as full IHI0098 compliance.
Current non-goals include:
Open issues
LCN support is an open design issue. In CHI C2C(actually, this is a CMN function), LCN is an HN-side function that allows a local domain to cache remote addresses; conceptually it behaves like an extra cache level between the Remote HN and the Local RN. The current branch models C2C gateway traversal, remote-sharer tracking, snoop routing, packetization, and credit timing, but it does not yet model an LCN as an HN-side cache for remote-home lines. I would like maintainer feedback on whether LCN should be modeled as an extension of the CHI home-node path, as a separate cache-like Ruby controller adjacent to the C2C gateway, or as follow-on work after the basic gateway and transport support are upstreamed.
Validation coverage
The current validation set covers the main protocol and transport surfaces:
cd tests && ./main.py run tests/gem5/chi_c2cSeriesGetx,SeriesGets,SeriesGetMixed, andInvalidatetraffic through a two-chip topology with packetizer bridges and deferred credit returns../build/ARM/gem5.opt tests/gem5/chi_c2c/configs/chi_c2c_run.py --test-type SeriesGetMixed --requests 100 --topology=Crossbar./build/ARM/gem5.opt tests/gem5/chi_c2c/configs/chi_c2c_run.py --test-type Invalidate --requests 100 --num-cpus 4 --topology=CrossbarReadSharedmerging before traffic enters the C2C path; this is local Ruby optimization coverage, not CHI C2C protocol coverage../build/ARM/gem5.opt tests/gem5/chi_c2c/configs/chi_c2c_run.py --test-type SeriesGetMixed --requests 100 --enable-read-mergeruby_mem_teststress./build/ARM/gem5.opt tests/gem5/chi_c2c/configs/chi_c2c_ruby_mem_test.py --topology R2 --num-cpus 4 --abs-max-tick 10000000000ruby_mem_teststress./build/ARM/gem5.opt tests/gem5/chi_c2c/configs/chi_c2c_ruby_mem_test.py --topology R3 --num-cpus 4 --num-c2cgs 3 --abs-max-tick 10000000000./build/ARM/gem5.opt tests/gem5/chi_c2c/configs/chi_c2c_ruby_mem_test.py --topology R3 --num-cpus 4 --num-c2cgs 3 --atomic 100 --abs-max-tick 1000000scons build/ARM/mem/ruby/protocol/chi/c2c/C2CPacketizer.test.opt && ./build/ARM/mem/ruby/protocol/chi/c2c/C2CPacketizer.test.optruby_mem_testruns../build/ARM/gem5.opt tests/gem5/chi_c2c/configs/chi_c2c_run.py --test-type SeriesGetMixed --requests 100./build/ARM/gem5.opt tests/gem5/chi_c2c/configs/chi_c2c_se.py <workload arguments>That does not mean the work is finished, but it does mean the discussion can be about upstream scope, interfaces, and review shape rather than only raw feasibility.
What seems upstreamable first
My current view is that this should be split into a few reviewable layers.
1. Core CHI C2C modeling support
CHI_C2Ccontroller,2. Transport and packetization support
C2CPacketizerBridge,3. Optional follow-on work
My bias would be to discuss layers 1 and 2 as the initial upstream target and treat layer 3 as follow-on work unless maintainers want a broader first series.
Questions for maintainers and CHI modelers
I would especially value feedback on the following:
CHI_C2Ccontroller the right architectural boundary?If there is interest, the next step would be to break this into a concrete patch plan with a minimal initial subset, explicit non-goals, and tests that make that subset reviewable.
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