RISCV 32 bits in SE mode

[maemilia811]

Hi,

I'm trying to run a simulation in SE mode for riscv 32 bits, the host is M2 Apple (gem5 version 25.0.0.1). I have the binary I want to simulate that has been compiled statically for riscv32 using musl C library inside a docker container with linux environment, but I get an error 'bad_alloc' due of writev syscall. I also tried to compile the binary using glibc and newlib but the same I get errors related with rseq syscall and page fault.
Is it possible to run this kind of simulation in SE mode?
Also I'm not sure if the configuration is correct for this case (see file attached). I paste the configuration here as well:

from pathlib import Path

from O3_RISCV import *

from m5.objects import *

import gem5.simulate.simulator as Sim
from gem5.components.boards.riscv_board import RiscvBoard
from gem5.components.cachehierarchies.classic.private_l1_private_l2_walk_cache_hierarchy import (
    PrivateL1PrivateL2WalkCacheHierarchy,
)
from gem5.components.memory.single_channel import SingleChannelDDR4_2400
from gem5.components.processors.base_cpu_core import BaseCPUCore
from gem5.components.processors.base_cpu_processor import BaseCPUProcessor
from gem5.isas import ISA
from gem5.resources.resource import BinaryResource

cache_hierarchy = PrivateL1PrivateL2WalkCacheHierarchy(
    l1d_size="32KiB",
    l1i_size="32KiB",
    l2_size="512KiB",
)

memory = SingleChannelDDR4_2400(size="3GiB")

custom_cpu_instance = O3_RISCV_CPU()

for isa in custom_cpu_instance.isa:
    isa.riscv_type = "RV32"

wrapped_core = BaseCPUCore(core=custom_cpu_instance, isa=ISA.RISCV)
processor = BaseCPUProcessor(cores=[wrapped_core])

board = RiscvBoard(
    clk_freq="3GHz",
    processor=processor,
    memory=memory,
    cache_hierarchy=cache_hierarchy,
)

binary_path = "gimli/gimli_riscv32"
board.set_se_binary_workload(BinaryResource(local_path=binary_path))

sim = Sim.Simulator(board=board)
sim.run()

Thank you in advance.

Maria
config_se_riscv.py

[powerjg]

Hi Maria,

The issue you are seeing with rseq and the resulting bad_alloc is a known limitation in gem5 v25.0.0.1. In that specific release, Syscall Emulation (SE) mode doesn't support or stub out the rseq (Restartable Sequences) system call for RISC-V. Modern toolchains and standard libraries (including musl and glibc) query sys_rseq during early initialization. Because v25.0.0.1 doesn't handle this properly, it leads to memory corruption or unhandled faults right as the binary spins up.

The clean solution here is to update your gem5 repository to the latest release (v25.1.0.0 or later). This issue was officially addressed in pull request #2525, which forces the simulator to gracefully ignore rseq on RISC-V and return -ENOSYS, allowing modern standard libraries to safely fall back and continue executing normally.

If you'd like to trace the exact system call sequence right before it crashes to double-check, you can run your script with the SyscallAll debug flag:

gem5.opt --debug-flags=SyscallAll config_se_riscv.py

Updating your gem5 build should clear this right up. Let us know if pulling the latest version fixes the crash for you!