Seeking Advice on Belady Cache Replacement Policy implementation and Simulating temporal/non-temporal cache separation

[dane73]

Hello,

I am currently working on my bachelor thesis, which compares cache replacement policies in the context of sparse matrix-vector multiplication (SpMV). My thesis has two subgoals:

1. Implement the Belady min algorithm as a cache replacement policy

My approach is a two-pass simulation: first record the sequence of cache block addresses, then re-run with a Bélády replacement policy that uses the recorded trace to always evict the block whose next use is furthest in the future.

First I tried to use the TraceCPU. But this did not work. As far as I understand, the O3CPU (on which TraceCPU is based) reorders memory accesses, for example by issuing other requests after a cache miss, so the address access order in the trace does not match the order in which addresses actually arrive at the cache. This makes it impossible to use a static recorded trace for Bélády CPR with TraceCPU?

Then I switched a AtomicSimpleCPU setup with a private l1 cache hierarchy. I recorded the incoming cache block addresses in BaseCache::recvAtomic. Then in in a second simulation, I re-run it with the Belady CRP that I implemented. As far as I can tell, this works well.

Q1: Is my assumption correct, that the AtomicSimpleCPU is deterministic? Will it always produces the same cache access sequence for the same binary and configuration?
Q2: Is BaseCache::recvAtomic a good spot to record the trace?
Q3: Are there any other pitfalls or gotchas I should be aware of with this approach?

If there is interest, I would love to form a PR, after incorporating any feedback.

2. Simulate temporal/non-temporal cache separation

The second part of my thesis analyzes an optimization technique that separates data into temporal (reused soon) and non-temporal (streaming, not reused) categories, storing them in separate cache partitions to avoid cache pollution. This is conceptually similar to the sector cache feature of the Fujitsu A64FX.

Q4: Is there a way to signal from within the simulated application which partition an access should be allocated into — for example via m5ops? I am aware of the WayPartitioningPolicy, but it appears to only support static partitioning configured at setup time rather than runtime hints from a running workload.

Q5: As an alternative to cache partitions, could I use two l1d caches? How would I do that?
Q6: Can this work with the AtomicSimpleCPU?

For my purposes I do not need a detailed microarchitectural simulation, so I am trying the keep the simulation as simple as possible by using the AtomicSimpleCPU with a single level of caches.

Thank you in advance.