gem5
L1D cache pmu count not matching with Arm coretex-a55 pmu count. #3251
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pmmidhunpam
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L1D cache pmu count not matching with Arm cortex-a55 pmu count for non-cache memory access.
Why gem5 pmu event (0x13) is high compared to real arm cortex-a55 event count
any configuration or options need to configure to model to match with cortex a-55 non-cache behaviour.?
Can you please share the gem5 configuration which need to configure for simulate ARM cortex-a55 arch .?
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