LiteX VexRiscV port?

[dwt]

Hi there,

while searching for this, we found two started but not completed ports of Micropython to this architecture:

• https://github.com/litex-hub/micropython/tree/litex-rebase
• https://github.com/gregdavill/circuitpython/tree/orangecrab

For both we couldn't find the reason why they stopped and have not been merged upstream.

Is there a reason why they wouldn't be mergeable? Is there some policy that prohibits their integration? Are there other known reasons why that work stopped?

Thank you very much for any information.

[Josverl]

Is there a reason why they wouldn't be mergeable?

Not impossible, but there have been a lot of changes since, so it would require a lot more work than a simple rebase.
New ports do require active development from the team that wants to add that port, there is not central team that will do the work for you.

MicroPython now defines port Tier levels, which categorizes the 20 existing ports into four groups according to their stage of development. This aims to set expectations for the level of support and development each port receives. And also lower the bar of entry for new ports so they can enter at a low Tier and gradually rise up to Tier 1. See the top-level README.md and the docs at https://docs.micropython.org/en/latest/develop/support_tiers.html

[jonnor]

Have you tried using the Zephyr port in MicroPython? LiteX has Zephyr support. Theoretically that would work without needing a LiteX specific port.

[jonnor]

Interesting! Was it Zephyr on LiteX that was the problem? Or Zephyr with MicroPython? At least the latter we can probably try to help with. I am still a LiteX noob - working on getting things to work on the C level before I try MicroPython.

I think that even with custom modules, it might be nice to share some things with. A Zephyr-LiteX thing will likely be a custom build of MicroPython - not something one uses as prebuilt image from micropython downloads page.
But I see the point. And this will in practice be up to those that actually do the work to choose how to approach it!

[dwt]

@jonnor If you are still getting things to work, we did achieve a C-level toolchain. I have a GitHub repo with a nix-expression that should nail down almost everything needed to get this to work.. This includes a C-Compiler that generates the correct floating point emulation for this platforms, and a full Litex toolchain and dependencies to get this working. All pinned down via NixPKGs where possible or fetched via shell scripts where not. I would love some feedback where your way differs - or perhaps pointers where we forgot to document a crucial step.

[jonnor]

I have a full toolchain/environment setup for both LiteX and Zephyr. I was able to build a Zephyr-based firmware, but did not get it to run correctly. I may need to set up GDB to observe what is going on. Will work on this for a couple of hours a week over the next couple of weeks.
I am using an ICE40 board. Working notes here, https://github.com/jonnor/embeddedml/tree/master/handson/fpga-riscv

[jonnor]

Got Zephyr working now, as well as GDB. Finding the ICE40 to be quite limiting though in terms of number of gates, so have also gotten myself a Gatemate. Next step is trying to build+run MicroPython with Zephyr port as the HAL.

[dwt]

Nice and congrats! I'll look into this when I continue with my project. We tried Zephyr and didn't get very far, but with what we know now, this may be much more feasible.

[Josverl]

Not sure what type of hardware you are considering , but I notice on
https://github.com/litex-hub/litex-boards?tab=readme-ov-file#-supported-boards

Note: All boards with >= 32MB of memory and enough logic can be considered as Linux Capable, have a look at Linux-on-LiteX-Vexriscv project to try Linux on your FPGA board!

so depending on your BOM, you could possibly just run the unix port ?

[dwt]

Yes, we tried that and it works (128mb RAM). However, adding custom VGA Hardware support on linux looks like a lot less fun than on MicroPython running natively.

This may be too stubborn, but that is the goal we started with.

[dwt]

That being said, building linux to actually run on this thing is apparently not simple, and the prebuilt binaries that project offers are... old and just binary blobs. We would really like to document how to build everything from source.

[Josverl]

Thanks for clarifying, could you give an example of the the hardware that you target to run under LiteX?
as there are 100+ LiteX supported boards, narrowing down the target would be useful.

[dwt]

All our documentation is here https://github.com/dwt/fpga-riscv we are targeting the OrangeCrab 85F board.