pccx-FPGA-NPU-LLM-kv260 v0.1.0-alpha — KV260 RTL preview snapshot

[hkimw]

The bare-metal Kria KV260 implementation of the pccx v002 NPU — RTL,
driver scaffolding, and verification harness — is now public as a
v0.1.0-alpha preview.

What this alpha is

A reference RTL preview, not a timing-closed bitstream. The
architecture spec is canonical at the
pccx Sphinx site;
this repo implements what that spec describes and ships an early
verification surface.

What's included

• SystemVerilog RTL of the v002 NPU top wrapper and all major blocks
  under hw/rtl/ (NPU controller, MAT/VEC/CVO cores, MEM control,
  preprocess pipeline).
• xsim verification harness at hw/sim/run_verification.sh plus
  testbenches covering the GEMM W4A8 packer / sign-recovery / weight
  dispatcher, the 48-bit normalizer, the result packer, the BF16
  barrel shifter, and the front-end decoder.
• Sail ISA model — types, regs, decode, and execute increments 1 to
  3. CI installs z3 and runs the Sail typecheck workflow on every
  PR.
• repo-validate required check on main (URL hygiene, brand-name
  guard, license / citation sanity).
• Stage 1/2/3 ruleset blocks direct push to main.

Known limitations

• No timing closure, no bitstream, no KV260 board bring-up artifacts.
• Sail model covers decode and the first three execute increments
  only.
• tb_GEMM_fmap_staggered_delay (shift-chain timing model) is parked
  WIP and not part of CI.
• No bit-accurate co-simulation harness with pccx-lab yet — that
  bridge lands in v0.2.0.
• The repository Wiki is intentionally empty. RTL and bring-up
  questions belong in Discussions; architectural docs live on the
  pccx Sphinx site.

Where to contribute

• Discussions (board bring-up, RTL Q&A, verification ideas):
  https://github.com/pccxai/pccx-FPGA-NPU-LLM-kv260/discussions
• Good first issues:
  good first issue Suitable for first-time contributors
• Roadmap: PCCX Roadmap
• Contributing guide:
  https://github.com/pccxai/.github/blob/main/CONTRIBUTING.md

Roadmap

• v0.2.0 ("Bring-up and closure") — complete remaining Sail execute
  increments, expand testbench coverage, post the first board
  bring-up logs, integrate the driver path with pccx-lab, and ship
  a timing-closed bitstream candidate.

Release link

https://github.com/pccxai/pccx-FPGA-NPU-LLM-kv260/releases/tag/v0.1.0-alpha