A fully pipelined RISC-V (RV32I) processor with L1 cache, built incrementally across six phases.
Contributors: Orion Brown, Kai Sprunger, Dawn Balaschak, Eren Durham
The project was developed in six phases, each building directly on the last:
| Phase | Description |
|---|---|
| 1 | Familiarization — tools, simulation environment setup |
| 2 | RISC-V assembler in C++ — encodes RV32I instructions to binary |
| 3 | ALU design in Verilog — arithmetic, logic, shifting, comparison |
| 4 | Single-cycle processor — full RV32I datapath with control unit |
| 5 | 5-stage pipeline — IF/ID/EX/MEM/WB with hazard detection and data forwarding |
| 6 | L1 cache — direct-mapped instruction and data caches with miss handling |
├── main.cpp / read_asm.cpp / rv32i.h # Phase 2: assembler
├── ALU.v / ALU_CONTROL.v # ALU and control logic
├── DECODER.v / REGISTER.v # Instruction decode and register file
├── CONTROL.v / BRANCH_JUMP.v # Main control unit and branching
├── DATA_MEMORY.v / INSTRUCTION_MEMORY.v
├── barrel_shifter.v / new_barrel.v # Barrel shifter implementations
├── IF_ID.v / ID_EX.v / EX_MEM.v / MEM_WB.v # Pipeline stage registers
├── hazard_detect.v / ForwardingUnit.v # Hazard detection and forwarding
├── CACHE.v / miss_handler.v # L1 cache and miss handler
├── REPLACE_POLICY.v / shared_mem.v # Cache replacement and backing memory
├── RISCV_TOP.v # Top-level integration
├── assembler.cpp # Phase 5/6 assembler
└── *.s # Test assembly programs
- RV32I ISA — supports R, I, S, B, U, and J instruction types
- 5-stage pipeline — handles data hazards via forwarding and stalls
- L1 cache — reduces memory access latency with configurable replacement policy
- Modular design — each component (ALU, decoder, memory) is independently testable
- Simulation: Icarus Verilog (
iverilog) + GTKWave - Assembler: compiled with
g++(g++ assembler.cpp -o assembler)