Skip to content

Pulling SIMs release 1.5.6 into main. #128

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 1 commit into from
Oct 6, 2024
Merged

Pulling SIMs release 1.5.6 into main. #128

Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
50 changes: 47 additions & 3 deletions sim_models/verilog/DLY_VALUE_MUX.v
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -8,12 +8,56 @@
//

module DLY_VALUE_MUX (
input [5:0] DLY_TAP_VAL_ARRAY[19:0], // 20 Delay Tap Value Input Ports
input [5:0] DLY_TAP0_VAL, // Delay Tap Value Input Port
input [5:0] DLY_TAP1_VAL, // Delay Tap Value Input Port
input [5:0] DLY_TAP2_VAL, // Delay Tap Value Input Port
input [5:0] DLY_TAP3_VAL, // Delay Tap Value Input Port
input [5:0] DLY_TAP4_VAL, // Delay Tap Value Input Port
input [5:0] DLY_TAP5_VAL, // Delay Tap Value Input Port
input [5:0] DLY_TAP6_VAL, // Delay Tap Value Input Port
input [5:0] DLY_TAP7_VAL, // Delay Tap Value Input Port
input [5:0] DLY_TAP8_VAL, // Delay Tap Value Input Port
input [5:0] DLY_TAP9_VAL, // Delay Tap Value Input Port
input [5:0] DLY_TAP10_VAL, // Delay Tap Value Input Port
input [5:0] DLY_TAP11_VAL, // Delay Tap Value Input Port
input [5:0] DLY_TAP12_VAL, // Delay Tap Value Input Port
input [5:0] DLY_TAP13_VAL, // Delay Tap Value Input Port
input [5:0] DLY_TAP14_VAL, // Delay Tap Value Input Port
input [5:0] DLY_TAP15_VAL, // Delay Tap Value Input Port
input [5:0] DLY_TAP16_VAL, // Delay Tap Value Input Port
input [5:0] DLY_TAP17_VAL, // Delay Tap Value Input Port
input [5:0] DLY_TAP18_VAL, // Delay Tap Value Input Port
input [5:0] DLY_TAP19_VAL, // Delay Tap Value Input Port
input [4:0] DLY_ADDR, // Input Address
output [5:0] DLY_TAP_VALUE // Delay Tap Value Output Port
output reg [5:0] DLY_TAP_VALUE // Delay Tap Value Output Port
);

assign DLY_TAP_VALUE= (DLY_ADDR<20)?DLY_TAP_VAL_ARRAY[DLY_ADDR]:5'd0;
always@(*)
begin
case(DLY_ADDR)
5'd0: DLY_TAP_VALUE = DLY_TAP0_VAL;
5'd1: DLY_TAP_VALUE = DLY_TAP1_VAL;
5'd2: DLY_TAP_VALUE = DLY_TAP2_VAL;
5'd3: DLY_TAP_VALUE = DLY_TAP3_VAL;
5'd4: DLY_TAP_VALUE = DLY_TAP4_VAL;
5'd5: DLY_TAP_VALUE = DLY_TAP5_VAL;
5'd6: DLY_TAP_VALUE = DLY_TAP6_VAL;
5'd7: DLY_TAP_VALUE = DLY_TAP7_VAL;
5'd8: DLY_TAP_VALUE = DLY_TAP8_VAL;
5'd9: DLY_TAP_VALUE = DLY_TAP9_VAL;
5'd10: DLY_TAP_VALUE = DLY_TAP10_VAL;
5'd11: DLY_TAP_VALUE = DLY_TAP11_VAL;
5'd12: DLY_TAP_VALUE = DLY_TAP12_VAL;
5'd13: DLY_TAP_VALUE = DLY_TAP13_VAL;
5'd14: DLY_TAP_VALUE = DLY_TAP14_VAL;
5'd15: DLY_TAP_VALUE = DLY_TAP15_VAL;
5'd16: DLY_TAP_VALUE = DLY_TAP16_VAL;
5'd17: DLY_TAP_VALUE = DLY_TAP17_VAL;
5'd18: DLY_TAP_VALUE = DLY_TAP18_VAL;
5'd19: DLY_TAP_VALUE = DLY_TAP19_VAL;
default: DLY_TAP_VALUE = 5'd0;
endcase
end

endmodule
`endcelldefine