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Merged
merged 3 commits into from
Oct 6, 2024
Merged

Added SIM change files from 1.5.6 #129

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116c7d4
Added SIM change files from 1.5.6
NadeemYaseen Oct 2, 2024
71a4d4e
DLY_SEL_DECODER tb updated
moinijaz Oct 3, 2024
5a4aa09
DLY_VALUE_MUX tb updated
moinijaz Oct 3, 2024
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44 changes: 41 additions & 3 deletions blackbox_models/cell_sim_blackbox.v
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Original file line number Diff line number Diff line change
Expand Up @@ -94,7 +94,26 @@ module DLY_SEL_DCODER (
input logic DLY_ADJ,
input logic DLY_INCDEC,
input logic [4:0] DLY_ADDR,
output reg [2:0] DLY_CNTRL[31:0]
output reg [2:0] DLY0_CNTRL,
output reg [2:0] DLY1_CNTRL,
output reg [2:0] DLY2_CNTRL,
output reg [2:0] DLY3_CNTRL,
output reg [2:0] DLY4_CNTRL,
output reg [2:0] DLY5_CNTRL,
output reg [2:0] DLY6_CNTRL,
output reg [2:0] DLY7_CNTRL,
output reg [2:0] DLY8_CNTRL,
output reg [2:0] DLY9_CNTRL,
output reg [2:0] DLY10_CNTRL,
output reg [2:0] DLY11_CNTRL,
output reg [2:0] DLY12_CNTRL,
output reg [2:0] DLY13_CNTRL,
output reg [2:0] DLY14_CNTRL,
output reg [2:0] DLY15_CNTRL,
output reg [2:0] DLY16_CNTRL,
output reg [2:0] DLY17_CNTRL,
output reg [2:0] DLY18_CNTRL,
output reg [2:0] DLY19_CNTRL
);
endmodule
`endcelldefine
Expand All @@ -107,9 +126,28 @@ endmodule
`celldefine
(* blackbox *)
module DLY_VALUE_MUX (
input logic [5:0] DLY_TAP_VAL_ARRAY[19:0],
input logic [5:0] DLY_TAP0_VAL,
input logic [5:0] DLY_TAP1_VAL,
input logic [5:0] DLY_TAP2_VAL,
input logic [5:0] DLY_TAP3_VAL,
input logic [5:0] DLY_TAP4_VAL,
input logic [5:0] DLY_TAP5_VAL,
input logic [5:0] DLY_TAP6_VAL,
input logic [5:0] DLY_TAP7_VAL,
input logic [5:0] DLY_TAP8_VAL,
input logic [5:0] DLY_TAP9_VAL,
input logic [5:0] DLY_TAP10_VAL,
input logic [5:0] DLY_TAP11_VAL,
input logic [5:0] DLY_TAP12_VAL,
input logic [5:0] DLY_TAP13_VAL,
input logic [5:0] DLY_TAP14_VAL,
input logic [5:0] DLY_TAP15_VAL,
input logic [5:0] DLY_TAP16_VAL,
input logic [5:0] DLY_TAP17_VAL,
input logic [5:0] DLY_TAP18_VAL,
input logic [5:0] DLY_TAP19_VAL,
input logic [4:0] DLY_ADDR,
output logic [5:0] DLY_TAP_VALUE
output reg [5:0] DLY_TAP_VALUE
);
endmodule
`endcelldefine
Expand Down
223 changes: 176 additions & 47 deletions sim_models/tb/DLY_SEL_DECODER_tb.v
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Expand Up @@ -4,62 +4,191 @@ module DLY_SEL_DCODER_tb;
// Parameters

//Ports
reg DLY_LOAD;
reg DLY_ADJ;
reg DLY_INCDEC;
reg DLY_LOAD;
reg DLY_ADJ;
reg DLY_INCDEC;
reg [4:0] DLY_ADDR;
wire [2:0] DLY_CNTRL[31:0];
wire [2:0] DLY0_CNTRL;
wire [2:0] DLY1_CNTRL;
wire [2:0] DLY2_CNTRL;
wire [2:0] DLY3_CNTRL;
wire [2:0] DLY4_CNTRL;
wire [2:0] DLY5_CNTRL;
wire [2:0] DLY6_CNTRL;
wire [2:0] DLY7_CNTRL;
wire [2:0] DLY8_CNTRL;
wire [2:0] DLY9_CNTRL;
wire [2:0] DLY10_CNTRL;
wire [2:0] DLY11_CNTRL;
wire [2:0] DLY12_CNTRL;
wire [2:0] DLY13_CNTRL;
wire [2:0] DLY14_CNTRL;
wire [2:0] DLY15_CNTRL;
wire [2:0] DLY16_CNTRL;
wire [2:0] DLY17_CNTRL;
wire [2:0] DLY18_CNTRL;
wire [2:0] DLY19_CNTRL;

integer error=0;

DLY_SEL_DCODER DLY_SEL_DCODER_inst (
.DLY_LOAD(DLY_LOAD),
.DLY_ADJ(DLY_ADJ),
.DLY_INCDEC(DLY_INCDEC),
.DLY_ADDR(DLY_ADDR),
.DLY_CNTRL(DLY_CNTRL)
.DLY0_CNTRL(DLY0_CNTRL),
.DLY1_CNTRL(DLY1_CNTRL),
.DLY2_CNTRL(DLY2_CNTRL),
.DLY3_CNTRL(DLY3_CNTRL),
.DLY4_CNTRL(DLY4_CNTRL),
.DLY5_CNTRL(DLY5_CNTRL),
.DLY6_CNTRL(DLY6_CNTRL),
.DLY7_CNTRL(DLY7_CNTRL),
.DLY8_CNTRL(DLY8_CNTRL),
.DLY9_CNTRL(DLY9_CNTRL),
.DLY10_CNTRL(DLY10_CNTRL),
.DLY11_CNTRL(DLY11_CNTRL),
.DLY12_CNTRL(DLY12_CNTRL),
.DLY13_CNTRL(DLY13_CNTRL),
.DLY14_CNTRL(DLY14_CNTRL),
.DLY15_CNTRL(DLY15_CNTRL),
.DLY16_CNTRL(DLY16_CNTRL),
.DLY17_CNTRL(DLY17_CNTRL),
.DLY18_CNTRL(DLY18_CNTRL),
.DLY19_CNTRL(DLY19_CNTRL)
);


initial
begin
DLY_LOAD=0;
DLY_ADJ=0;
DLY_INCDEC=0;
DLY_ADDR=0;
#5;
repeat(5)
begin
DLY_LOAD=$urandom;
DLY_ADJ=$urandom;
DLY_INCDEC=$urandom;
DLY_ADDR=$urandom;
#10;
// $display("Bus Array Content:");
// for (integer i = 0; i < 32; i = i + 1) begin
// $display("DLY_CNTRL[%0d] = %b", i, DLY_CNTRL[i]);
// #2;
// end
if(DLY_ADDR<20)
begin
if(DLY_CNTRL[DLY_ADDR]==={DLY_LOAD, DLY_ADJ, DLY_INCDEC})
$display("Test Passed");
else
$display("Test Failed");
end
else
begin
if(DLY_CNTRL[DLY_ADDR]===3'b000)
$display("Test Passed");
else
$display("Test Failed");
end
#100;
end
#1000;
$finish;
end
initial
begin

initial
begin
DLY_LOAD=0;
DLY_ADJ=0;
DLY_INCDEC=0;
DLY_ADDR=0;
#5;
repeat(100)
begin
DLY_LOAD=$urandom;
DLY_ADJ=$urandom;
DLY_INCDEC=$urandom;
DLY_ADDR=$urandom;
#10;
if(DLY_ADDR===0)
begin
if(DLY0_CNTRL!=={DLY_LOAD, DLY_ADJ, DLY_INCDEC})
error++;
end

if(DLY_ADDR===1)
begin
if(DLY1_CNTRL!=={DLY_LOAD, DLY_ADJ, DLY_INCDEC})
error++;
end

if(DLY_ADDR===2)
begin
if(DLY2_CNTRL!=={DLY_LOAD, DLY_ADJ, DLY_INCDEC})
error++;
end
if(DLY_ADDR===3)
begin
if(DLY3_CNTRL!=={DLY_LOAD, DLY_ADJ, DLY_INCDEC})
error++;
end
if(DLY_ADDR===4)
begin
if(DLY4_CNTRL!=={DLY_LOAD, DLY_ADJ, DLY_INCDEC})
error++;
end
if(DLY_ADDR===5)
begin
if(DLY5_CNTRL!=={DLY_LOAD, DLY_ADJ, DLY_INCDEC})
error++;
end
if(DLY_ADDR===6)
begin
if(DLY6_CNTRL!=={DLY_LOAD, DLY_ADJ, DLY_INCDEC})
error++;
end
if(DLY_ADDR===7)
begin
if(DLY7_CNTRL!=={DLY_LOAD, DLY_ADJ, DLY_INCDEC})
error++;
end
if(DLY_ADDR===8)
begin
if(DLY8_CNTRL!=={DLY_LOAD, DLY_ADJ, DLY_INCDEC})
error++;
end
if(DLY_ADDR===9)
begin
if(DLY9_CNTRL!=={DLY_LOAD, DLY_ADJ, DLY_INCDEC})
error++;
end
if(DLY_ADDR===10)
begin
if(DLY10_CNTRL!=={DLY_LOAD, DLY_ADJ, DLY_INCDEC})
error++;
end
if(DLY_ADDR===11)
begin
if(DLY11_CNTRL!=={DLY_LOAD, DLY_ADJ, DLY_INCDEC})
error++;
end
if(DLY_ADDR===12)
begin
if(DLY12_CNTRL!=={DLY_LOAD, DLY_ADJ, DLY_INCDEC})
error++;
end
if(DLY_ADDR===13)
begin
if(DLY13_CNTRL!=={DLY_LOAD, DLY_ADJ, DLY_INCDEC})
error++;
end
if(DLY_ADDR===14)
begin
if(DLY14_CNTRL!=={DLY_LOAD, DLY_ADJ, DLY_INCDEC})
error++;
end
if(DLY_ADDR===15)
begin
if(DLY15_CNTRL!=={DLY_LOAD, DLY_ADJ, DLY_INCDEC})
error++;
end
if(DLY_ADDR===16)
begin
if(DLY16_CNTRL!=={DLY_LOAD, DLY_ADJ, DLY_INCDEC})
error++;
end
if(DLY_ADDR===17)
begin
if(DLY17_CNTRL!=={DLY_LOAD, DLY_ADJ, DLY_INCDEC})
error++;
end
if(DLY_ADDR===18)
begin
if(DLY18_CNTRL!=={DLY_LOAD, DLY_ADJ, DLY_INCDEC})
error++;
end
if(DLY_ADDR===19)
begin
if(DLY19_CNTRL!=={DLY_LOAD, DLY_ADJ, DLY_INCDEC})
error++;
end

#100;
end
if(error===0)
$display("Test Passed");
else
$display("Test Failed");
#1000;
$finish;
end
initial
begin
$dumpfile("waves.vcd");
$dumpvars;
end
endmodule
end
endmodule
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