Fail sim 1.5.8

sim_models/tb/MIPI_TX_tb.v

@@ -151,4 +151,4 @@ module MIPI_TX_tb;
     $dumpfile("waves.vcd");
     $dumpvars;
 	end
-endmodule
+endmodule

sim_models/tb/SOC_FPGA_INTF_IRQ_tb.v

@@ -0,0 +1,51 @@
+
+module SOC_FPGA_INTF_IRQ_tb;
+  reg IRQ_CLK;
+  reg IRQ_RST_N;
+  reg [3:0] IRQ_SRC;
+  wire [3:0] IRQ_SET;
+
+  reg [3:0] irq_src;
+
+    SOC_FPGA_INTF_IRQ soc_fpga_intf_irq(
+    .IRQ_SRC(IRQ_SRC),
+    .IRQ_SET(IRQ_SET),
+    .IRQ_CLK(IRQ_CLK),
+    .IRQ_RST_N(IRQ_RST_N)
+    );
+
+    initial begin
+      //generating clock
+      IRQ_CLK = 0;
+      forever #5 IRQ_CLK = ~IRQ_CLK;
+    end
+
+    initial begin
+      IRQ_SRC = 0;
+      IRQ_RST_N = 0;
+
+      repeat(2) @(posedge IRQ_CLK);
+      IRQ_RST_N = 1;
+
+      for (int i=0; i<10; i++) begin
+        IRQ_SRC = $random();
+        @(posedge IRQ_CLK);
+      end
+
+      $finish;
+
+    end
+
+    always @(posedge IRQ_CLK) irq_src <= IRQ_SRC;
+
+    initial begin 
+      forever begin
+        if(IRQ_RST_N)
+         if (IRQ_SET == irq_src) 
+          $info("True IRQ_SET");
+         else $error("False IRQ_SET %0d , IRQ_SRC %0d ", IRQ_SET ,irq_src );
+        @(posedge IRQ_CLK);
+      end
+    end
+
+endmodule

sim_models/tb/SOC_FPGA_INTF_JTAG_tb.v

@@ -0,0 +1,71 @@
+`timescale 1ns/1ps
+
+module SOC_FPGA_INTF_JTAG_tb;
+
+  // Inputs
+  reg BOOT_JTAG_TCK;
+  reg BOOT_JTAG_TDO;
+  reg BOOT_JTAG_EN;
+
+  // Outputs
+  wire BOOT_JTAG_TDI;
+  wire BOOT_JTAG_TMS;
+  wire BOOT_JTAG_TRSTN;
+
+  reg [3:0] tdo;
+
+  SOC_FPGA_INTF_JTAG dut (
+    .BOOT_JTAG_TCK(BOOT_JTAG_TCK),
+    .BOOT_JTAG_TDI(BOOT_JTAG_TDI),
+    .BOOT_JTAG_TDO(BOOT_JTAG_TDO),
+    .BOOT_JTAG_TMS(BOOT_JTAG_TMS),
+    .BOOT_JTAG_TRSTN(BOOT_JTAG_TRSTN),
+    .BOOT_JTAG_EN(BOOT_JTAG_EN)
+  );
+
+
+  initial begin
+    BOOT_JTAG_TCK = 0;
+    forever #5 BOOT_JTAG_TCK = ~BOOT_JTAG_TCK;
+  end
+
+
+  // Stimulus
+  initial begin
+
+    BOOT_JTAG_TDO = 1'b0;
+    BOOT_JTAG_EN = 1'b0;
+
+    #10;
+
+    for (int i=0; i<10; i++) begin
+        BOOT_JTAG_TDO = ~BOOT_JTAG_TDO;
+      @(posedge BOOT_JTAG_TCK);
+    end
+
+    #10;
+
+    BOOT_JTAG_EN = 1'b1;
+
+    for (int i=0; i<10; i++) begin
+        BOOT_JTAG_TDO = ~BOOT_JTAG_TDO;
+      @(posedge BOOT_JTAG_TCK);
+    end
+
+    #10;
+    $finish;
+  end
+
+  always @(posedge BOOT_JTAG_TCK) tdo <= BOOT_JTAG_TDO;
+
+    initial begin 
+      forever begin
+        if(BOOT_JTAG_TRSTN && BOOT_JTAG_TMS)
+         if (BOOT_JTAG_TDI == tdo) 
+          $info("True BOOT_JTAG_TDI");
+         else $error("False BOOT_JTAG_TDI %0d , BOOT_JTAG_TDO %0d ", BOOT_JTAG_TDI ,tdo );
+        @(posedge BOOT_JTAG_TCK);
+      end
+    end
+
+endmodule

specs_internal/DLY_SEL_DECODER.yaml

@@ -0,0 +1,144 @@
+# Periphery Primitives Parameters and Properties (P4)
+#
+# This file contains the list of Verilog parameters and SDC properties that are
+# allowed for periphery primitives.
+#
+# See https://rapidsilicon.atlassian.net/wiki/spaces/RS/pages/214368265/Periphery+Primitive+Parameters+and+Properties+Definitions+P4DEF for more details
+#
+# The name needs to match the filename root
+# name: <primitive name>
+# desc: <optional description>
+#
+# ports:
+#   <portname>:
+#       dir: <input, output, inout>
+#       desc: <optional description>
+#   <portname>:
+#       dir: <input, output, inout>
+#       desc: <optional description>
+#
+# # set as Verilog parameter
+# parameters:
+#    <parameter_name>:
+#        desc: <description>
+#        values:
+#          - <enum_name>
+#          - <enum_name>
+#    <parameter_name>:
+#        desc: <description>
+#        values:
+#          - <enum_name>
+#          - <enum_name>  
+#
+# # set in SDC or by synthesis attribute
+# properties:
+#    <property_name>:
+#        desc: <description>
+#        values: 
+#          - <enum_name>
+#          - <enum_name>
+#    <property_name>:
+#        desc: <description>
+#          - <enum_name>
+#          - <enum_name>
+#
+# primitive name should match the filename root.
+name: DLY_SEL_DECODER
+desc: Address Decoder
+category: periphery
+timescale: 1ps/1ps
+
+ports:
+   DLY_LOAD:
+     dir: input
+     desc: Delay load input
+   DLY_ADJ:
+     dir: input
+     desc: Delay adjust input
+   DLY_INCDEC:
+     dir: input
+     desc: Delay increment / decrement input
+   DLY_ADDR[4:0]:
+     dir: input
+     desc: Input Address
+   DLY0_CNTRL[2:0]:
+     dir: output
+     desc: Output Bus
+     type: reg
+   DLY1_CNTRL[2:0]:
+     dir: output
+     desc: Output Bus
+     type: reg
+   DLY2_CNTRL[2:0]:
+     dir: output
+     desc: Output Bus
+     type: reg
+   DLY3_CNTRL[2:0]:
+     dir: output
+     desc: Output Bus
+     type: reg
+   DLY4_CNTRL[2:0]:
+     dir: output
+     desc: Output Bus
+     type: reg
+   DLY5_CNTRL[2:0]:
+     dir: output
+     desc: Output Bus
+     type: reg
+   DLY6_CNTRL[2:0]:
+     dir: output
+     desc: Output Bus
+     type: reg
+   DLY7_CNTRL[2:0]:
+     dir: output
+     desc: Output Bus
+     type: reg
+   DLY8_CNTRL[2:0]:
+     dir: output
+     desc: Output Bus
+     type: reg
+   DLY9_CNTRL[2:0]:
+     dir: output
+     desc: Output Bus
+     type: reg
+   DLY10_CNTRL[2:0]:
+     dir: output
+     desc: Output Bus
+     type: reg
+   DLY11_CNTRL[2:0]:
+     dir: output
+     desc: Output Bus
+     type: reg
+   DLY12_CNTRL[2:0]:
+     dir: output
+     desc: Output Bus
+     type: reg
+   DLY13_CNTRL[2:0]:
+     dir: output
+     desc: Output Bus
+     type: reg
+   DLY14_CNTRL[2:0]:
+     dir: output
+     desc: Output Bus
+     type: reg
+   DLY15_CNTRL[2:0]:
+     dir: output
+     desc: Output Bus
+     type: reg
+   DLY16_CNTRL[2:0]:
+     dir: output
+     desc: Output Bus
+     type: reg
+   DLY17_CNTRL[2:0]:
+     dir: output
+     desc: Output Bus
+     type: reg
+   DLY18_CNTRL[2:0]:
+     dir: output
+     desc: Output Bus
+     type: reg
+   DLY19_CNTRL[2:0]:
+     dir: output
+     desc: Output Bus
+     type: reg
+