Virgo soc spi flash support

[junaidaslamRS]

• Introduced a Memory Parent Node to create a simple-bus for making SPI build pass.
• Corrected the SPI interface clock from 26.6MHz to 13.3MHz in board DTS. [We need to correct the reference in EmbeddedCommon-Dev too]
• Changed one of the values in SFDP Header to specify the correct sector erase command as per our soc prototype flash chip.
• Erase, Read, Write all working ok now.

[rahul-r-shah]

Actually these are not requests, but more some questions.

[rahul-r-shah]

Suggested change

	ilm: memory@A0200060 {
	ilm: memory@A0200060 {

Should the address be A0200060 or A0200000?

[junaidaslamRS]

We can definitely change it. Our FSBL binary is run from 0xA020005C because the first 5C bytes are taken by UBI header. The Zephyr binary address is kept 0xA0200060 due to alignment issues and also considering UBI header space.

If we know how Zephyr will be put in ILM, we can then think of its execution location accordingly.

[rahul-r-shah]

We can definitely change it. Our FSBL binary is run from 0xA020005C because the first 5C bytes are taken by UBI header. The Zephyr binary address is kept 0xA0200060 due to alignment issues and also considering UBI header space.

If we know how Zephyr will be put in ILM, we can then think of its execution location accordingly.

Ok, I understand you are suggesting that the binary will consist of the UBI header and the actual Zephyr binary too and we will be loading the entire binary into the ILM. But what about the BOP header of the zephyr binary.

Zephyr should be loaded the same way as FSBL. So the ways of loading are

1. Via openOCD (JTAG): Do we currently load the entire binary (UBI binary with BOP or only the zephyr binary?) and then jump to the FSBL (in this case zephyr)? In this case the loading happens via bootrom code and the FSBL (zephyr image will have to have code for FSBL in the BOP) will be loaded into the ILM (I believe the UBI and the BOP will be stripped and all the security operations, like authentication and decryption will be performed )
2. Via UART: In this case the CLI will be in XMODEM command and in this mode the unsecure binary will be downloaded
3. From Flash: In this case the bootrom will decrypt and authenticate (if secure) binary and then will load the FSBL (zephyr) in the load address

[junaidaslamRS]

At the moment, we are loading Zephyr using xmodem command on CLI over USART.

For loading Zephyr via Flash, we will have to use the same method which we use for FSBL on FLASH. Using OpenOCD we load everything on the flash. Then we reboot into SPI boot mode and bootrom then loads Zephyr, after security stuff, into the ILM. In this case, we will need a UBI header of the BOP which will have Zephyr as its binary.

[rahul-r-shah]

LGTM. Lets discuss the zephyr start location and make the modifications based on that discuss in future PRs