[PWCI] "[v5] acl: support custom memory allocators in rte_acl_build"

VERSION

@@ -1 +1 @@
-25.11.0-rc4
+25.11.0

app/test-bbdev/test_vectors/bbdev_null.data

@@ -2,4 +2,4 @@
 # Copyright(c) 2017 Intel Corporation
 
 op_type =
-RTE_BBDEV_OP_NONE
+RTE_BBDEV_OP_NONE

app/test-bbdev/test_vectors/turbo_dec_c1_k6144_r0_e10376_crc24b_sbd_negllr_high_snr.data

@@ -637,4 +637,4 @@ RTE_BBDEV_TURBO_SUBBLOCK_DEINTERLEAVE, RTE_BBDEV_TURBO_CRC_TYPE_24B,
 RTE_BBDEV_TURBO_NEG_LLR_1_BIT_IN
 
 expected_status =
-OK
+OK

app/test-bbdev/test_vectors/turbo_dec_c1_k6144_r0_e10376_crc24b_sbd_negllr_low_snr.data

@@ -637,4 +637,4 @@ RTE_BBDEV_TURBO_SUBBLOCK_DEINTERLEAVE, RTE_BBDEV_TURBO_CRC_TYPE_24B,
 RTE_BBDEV_TURBO_NEG_LLR_1_BIT_IN
 
 expected_status =
-OK
+OK

app/test-bbdev/test_vectors/turbo_dec_c1_k6144_r0_e34560_sbd_posllr.data

@@ -1219,4 +1219,4 @@ RTE_BBDEV_TURBO_SOFT_OUTPUT, RTE_BBDEV_TURBO_SUBBLOCK_DEINTERLEAVE, RTE_BBDEV_TU
 RTE_BBDEV_TURBO_NEG_LLR_1_BIT_SOFT_OUT
 
 expected_status =
-OK
+OK

app/test-bbdev/test_vectors/turbo_dec_c2_k3136_r0_e4920_sbd_negllr_crc24b.data

@@ -674,4 +674,4 @@ RTE_BBDEV_TURBO_SUBBLOCK_DEINTERLEAVE, RTE_BBDEV_TURBO_NEG_LLR_1_BIT_IN,
 RTE_BBDEV_TURBO_CRC_TYPE_24B, RTE_BBDEV_TURBO_DEC_TB_CRC_24B_KEEP
 
 expected_status =
-OK
+OK

app/test-bbdev/test_vectors/turbo_enc_c1_k6144_r0_e18448_crc24a.data

@@ -156,4 +156,4 @@ op_flags =
 RTE_BBDEV_TURBO_CRC_24A_ATTACH
 
 expected_status =
-OK
+OK

app/test-bbdev/test_vectors/turbo_enc_c3_k4800_r2_e14412_crc24b.data

@@ -150,4 +150,4 @@ op_flags =
 RTE_BBDEV_TURBO_CRC_24B_ATTACH
 
 expected_status =
-OK
+OK

app/test/test_acl.c

@@ -1721,6 +1721,125 @@ test_u32_range(void)
 	return rc;
 }
 
+struct acl_ctx_wrapper_t {
+	struct rte_acl_ctx *ctx;
+	void *running_buf;
+	bool running_buf_using;
+};
+
+#define ACL_RUNNING_BUF_SIZE (10 * 1024 * 1024)
+
+static void *running_alloc(void *udata, char *name, size_t size,
+	size_t align, int32_t socket_id)
+{
+	(void)align;
+	(void)name;
+	(void)socket_id;
+	if (size > ACL_RUNNING_BUF_SIZE)
+		return NULL;
+	struct acl_ctx_wrapper_t *gwlb_acl_ctx = (struct acl_ctx_wrapper_t *)udata;
+	if (gwlb_acl_ctx->running_buf_using)
+		return NULL;
+	printf("running memory alloc for acl context, size=%zu, pointer=%p\n",
+		size,
+		gwlb_acl_ctx->running_buf);
+	memset(gwlb_acl_ctx->running_buf, 0, size);
+	gwlb_acl_ctx->running_buf_using = true;
+	return gwlb_acl_ctx->running_buf;
+}
+
+static void running_free(void *udata, void *ptr)
+{
+	if (!ptr)
+		return;
+	struct acl_ctx_wrapper_t *gwlb_acl_ctx = (struct acl_ctx_wrapper_t *)udata;
+	printf("running memory free, pointer=%p\n", ptr);
+	gwlb_acl_ctx->running_buf_using = false;
+}
+
+static int
+test_mem_cb(void)
+{
+	int i, ret;
+	struct acl_ctx_wrapper_t g_acl_ctx_wrapper;
+	g_acl_ctx_wrapper.ctx = rte_acl_create(&acl_param);
+	if (g_acl_ctx_wrapper.ctx == NULL) {
+		printf("Line %i: Error creating ACL context!\n", __LINE__);
+		return -1;
+	}
+	g_acl_ctx_wrapper.running_buf = rte_zmalloc_socket(
+		"test_acl",
+		ACL_RUNNING_BUF_SIZE,
+		RTE_CACHE_LINE_SIZE,
+		SOCKET_ID_ANY);
+	if (!g_acl_ctx_wrapper.running_buf) {
+		printf("Line %i: Error allocing running buf for acl context!\n", __LINE__);
+		return 1;
+	}
+	g_acl_ctx_wrapper.running_buf_using = false;
+
+	struct rte_acl_mem_cb mcb = {
+		.zalloc = running_alloc,
+		.free = running_free,
+		.udata = &g_acl_ctx_wrapper
+	};
+	ret = rte_acl_set_mem_cb(g_acl_ctx_wrapper.ctx, &mcb);
+	if (ret) {
+		printf("Line %i: Error set mem cb for acl context!\n", __LINE__);
+		return 1;
+	}
+	struct rte_acl_mem_cb new_mcb;
+	memset(&new_mcb, 0, sizeof(struct rte_acl_mem_cb));
+	ret = rte_acl_get_mem_cb(g_acl_ctx_wrapper.ctx, &new_mcb);
+	if (ret) {
+		printf("Line %i: Error get mem cb for acl context!\n", __LINE__);
+		return 1;
+	}
+	if (memcmp(&mcb, &new_mcb, sizeof(struct rte_acl_mem_cb)) != 0) {
+		printf("Line %i: Error get mem cb for acl context!\n", __LINE__);
+		return 1;
+	}
+	ret = 0;
+	for (i = 0; i != TEST_CLASSIFY_ITER; i++) {
+
+		if ((i & 1) == 0)
+			rte_acl_reset(g_acl_ctx_wrapper.ctx);
+		else
+			rte_acl_reset_rules(g_acl_ctx_wrapper.ctx);
+
+		ret = test_classify_buid(g_acl_ctx_wrapper.ctx, acl_test_rules,
+			RTE_DIM(acl_test_rules));
+		if (ret != 0) {
+			printf("Line %i, iter: %d: "
+				"Adding rules to ACL context failed!\n",
+				__LINE__, i);
+			break;
+		}
+
+		ret = test_classify_run(g_acl_ctx_wrapper.ctx, acl_test_data,
+			RTE_DIM(acl_test_data));
+		if (ret != 0) {
+			printf("Line %i, iter: %d: %s failed!\n",
+				__LINE__, i, __func__);
+			break;
+		}
+
+		/* reset rules and make sure that classify still works ok. */
+		rte_acl_reset_rules(g_acl_ctx_wrapper.ctx);
+		ret = test_classify_run(g_acl_ctx_wrapper.ctx, acl_test_data,
+			RTE_DIM(acl_test_data));
+		if (ret != 0) {
+			printf("Line %i, iter: %d: %s failed!\n",
+				__LINE__, i, __func__);
+			break;
+		}
+	}
+
+	rte_acl_free(g_acl_ctx_wrapper.ctx);
+	rte_free(g_acl_ctx_wrapper.running_buf);
+	return ret;
+}
+
 static int
 test_acl(void)
 {
@@ -1742,6 +1861,8 @@ test_acl(void)
 		return -1;
 	if (test_u32_range() < 0)
 		return -1;
+	if (test_mem_cb() < 0)
+		return -1;
 
 	return 0;
 }

doc/guides/nics/cxgbe.rst

@@ -886,4 +886,3 @@ port.
 
 For this reason, one cannot allow/block a single port without
 allowing/blocking the other ports on the same device.
-

doc/guides/nics/ipn3ke.rst

@@ -88,7 +88,3 @@ To start ``testpmd``, and add I40e PF to FPGA network port, enable FPGA HQoS and
 .. code-block:: console
 
     ./<build_dir>/app/dpdk-testpmd -l 0-15 --vdev 'ifpga_rawdev_cfg0,ifpga=b3:00.0,port=0' --vdev 'ipn3ke_cfg0,afu=0|b3:00.0,fpga_acc={tm|flow},i40e_pf={0000:b1:00.0|0000:b1:00.1|0000:b1:00.2|0000:b1:00.3|0000:b5:00.0|0000:b5:00.1|0000:b5:00.2|0000:b5:00.3}' -- -i --no-numa --forward-mode=macswap
-
-Limitations or Known issues
----------------------------
-

doc/guides/nics/mlx5.rst

@@ -689,9 +689,11 @@ for an additional list of options shared with other mlx5 drivers.
 - ``dv_flow_en`` parameter [int]
 
   Value 0 means legacy Verbs flow offloading.
+  It is available for devices older than ConnectX-9.
 
-  Value 1 enables the DV flow steering assuming it is supported by the
-  driver (requires rdma-core 24 or higher).
+  Value 1 enables the Direct Verbs flow steering.
+  It is available for devices older than ConnectX-9,
+  and requires rdma-core 24 or later.
 
   Value 2 enables the WQE based hardware steering.
   In this mode, only queue-based flow management is supported.
@@ -1338,7 +1340,8 @@ Hardware Steering
 ~~~~~~~~~~~~~~~~~
 
 Faster than software steering (SWS),
-hardware steering (HWS) is the only mode supporting the flow template async API.
+hardware steering (HWS) is the only mode supporting the flow template async API,
+and the only mode supported on device ConnectX-9 and later.
 
 Flow rules are managed by the hardware,
 with a WQE-based high scaling and safer flow insertion/destruction.

drivers/event/dlb2/dlb2_iface.c

@@ -81,4 +81,3 @@ int (*dlb2_iface_set_cq_inflight_ctrl)(struct dlb2_hw_dev *handle,
 
 int (*dlb2_iface_set_cos_bw)(struct dlb2_hw_dev *handle,
 			     struct dlb2_set_cos_bw_args *args);
-

drivers/net/bnxt/tf_core/tf_em_common.c

@@ -20,4 +20,3 @@
 #include "tf_ext_flow_handle.h"
 #include "hcapi_cfa.h"
 #include "bnxt.h"
-

drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_act.c

@@ -261,4 +261,3 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
 	.act_tid = 12
 	}
 };
-

drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c

@@ -8362,4 +8362,3 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		},
 	}
 };
-

drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_defs.h

@@ -85,4 +85,3 @@ enum bnxt_ulp_template_id {
 };
 
 #endif
-

drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c

@@ -4065,4 +4065,3 @@ uint32_t ulp_act_prop_map_table[] = {
 	[BNXT_ULP_ACT_PROP_IDX_LAST] =
 		BNXT_ULP_ACT_PROP_SZ_LAST
 };
-

drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor2_class.c

@@ -68548,4 +68548,3 @@ struct bnxt_ulp_mapper_ident_info ulp_thor2_class_ident_list[] = {
 	.ident_bit_pos = 64
 	}
 };
-

drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c

@@ -69581,4 +69581,3 @@ struct bnxt_ulp_mapper_ident_info ulp_thor_class_ident_list[] = {
 	.ident_bit_pos = 62
 	}
 };
-

drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c

@@ -18776,4 +18776,3 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = {
 	.ident_bit_pos = 0
 	}
 };
-

drivers/net/gve/base/gve_adminq.c

@@ -1080,4 +1080,3 @@ int gve_adminq_configure_rss(struct gve_priv *priv,
 		gve_free_dma_mem(&rss_key_dma_mem);
 	return err;
 }
-

drivers/net/gve/gve_rss.c

@@ -203,4 +203,3 @@ gve_to_rte_rss_hf(uint16_t gve_rss_types, struct rte_eth_rss_conf *rss_conf)
 	if (gve_rss_types & GVE_RSS_HASH_UDPV6_EX)
 		rss_conf->rss_hf |= RTE_ETH_RSS_IPV6_UDP_EX;
 }
-