This repository is dedicated to building digital filter from mathematical model in MatLab Simulink to RTL and then to ASIC (IP-core) topology with Cadence tools such as RTL-Compiler, Encounter and Viruoso for final sign-off verification. The filter is a passband IIR-filter with x3 parallelization for higher operating sample frequency.
Filter characteristics are as follows (fs - sample frequency):
| Frequency, fs | Attenuation, dB | ||
| Passband center | 0.15 | Stopband attenuation | 65 |
| Passband center | 0.25 | Passband ripple | 0.25 |
| Transition bands | 0.05 |
Input/Output bit depth = 11 bits.
Synthesis constraints: Target sample frequency = 20 MHz, clock uncertanty (jitter) = 10%.
Filter's coefficients are calculated with MatLab's Filter Designer utility (fdatool).
The resulting filter is 12-th order elliptic filter.
Input samples are in fixed point representation so as arithmetics inside filter.
Every arithmetic block's output bit depth was minimized to to such an extent that the output of fixed point filter model had a maximum error from refence model of no more then 0.5 LSBs.
Filter's HDL-description is written in SystemVerilog, top-level architecture of this DSP-block is shown below.
(fs and fs/3 denotes sample rates at different stages of a design.)
Testing filter with chirp-like input signal results in desired frequency response.
Here is an image of a synthesized filter layout from Encounter with rulers.
ASIC layout dimensions are 1290
- /RTL,
- /Simulink.
First one contains everything related to rtl: final version of filter rtl-description, everything related to design synthesis (logical and physical).
Second subdirectory contains Simulink model files, result of HDL conversion by HDL Coder and a script for reference data generation for RTL-simulation.
Go to dedicated README's to find files descriptions and instructions on how to build project.