ECE 554 Mini Project repository

This repository contains the code for the mini projects for ECE 554 @ UW-Madison, Spring 2023.

Group members:

• Julien de Castelnau
• Elan Graupe

Building requirements

All of the mentioned programs should be in $PATH.

• make
• python3
• Modelsim: vsim
• Quartus executables: quartus_sh, quartus_pgm

How to build

• To build a SOF file for the DE1-SoC: make fpga
• To simulate all testbenches: make sim
• To simulate a specific testbench called MyTB (see Repository Structure): make sim TB=MyTB
• To open the modelsim GUI for MyTB: make gui TB=MyTB

I can't use the scripts. Where do I go?

• To open the quartus project: Double click the *.qsf in fpga/de1_soc.
  • Make sure the assembly file you want is built and placed in out/out.hex. See below simulation steps for building asm files.
• To simulate MiniLab0:
  • Create the ModelSim project manually. Add tb/MiniLab0/MiniLab0_tb.sv to the project. Add all of the files in rtl/ (the design files) to the project.
  • Create out/ in the root of the repository if it does not already exist.
  • From the root of the repository, run python3 sw/assemble.py fw/MiniLab0.asm -o out/out.hex.
  • Start simulation with MiniLab0_tb as the toplevel and run.

Repository Structure

• doc/: Contains all documentation related to the project.
• fpga/: Contains quartus projects for each board, having their own directory with a Makefile inside. For instance, fpga/de1_soc.
• fw/: Contains all firmware to be run on the FPGA itself. Assembly files, potentially C files in the future, etc.
• out/: A folder autogenerated by the scripts. The memory modules look for the instruction memory listing in this folder, out.hex.
• rtl/: Contains all of the synthesizable design logic.
• sw/: Accessory software to run on the host PC. Automation scripts live here. E.g assembler, testbench runner
• tb/: Contains a folder within for each testbench, plus a folder (tb/pkg/) for all packages containing tasks,functions,parameters, etc. for the testbenches.
• tb.json: A JSON file used by the automation scripts to associate each testbench folder with a top level Verilog module, and a firmware file to automatically build.