What if this edge has multiple clk with multiple clock latency cross this hierarchical pin ?

[icbenchpeng]

void
Sdc::annotateHierClkLatency()
{
ClockLatencies::Iterator latency_iter(clk_latencies_);
while (latency_iter.hasNext()) {
ClockLatency *latency = latency_iter.next();
const Pin *pin = latency->pin();
if (pin && network_->isHierarchical(pin))
annotateHierClkLatency(pin, latency);
}
}

void
Sdc::annotateHierClkLatency(const Pin *hpin,
ClockLatency *latency)
{
EdgesThruHierPinIterator edge_iter(hpin, network_, graph_);
while (edge_iter.hasNext()) {
Edge *edge = edge_iter.next();
edge_clk_latency_[edge] = latency;
}
}

[icbenchpeng]

What is the correct behaviour if meet multiple clks thruClkInfo ? should we also pass the clock to it ?

[akashlevy]

You should create a small test case clearly demonstrating the issue. In this case, it seems you believe that multiple clock latencies across two clocks would have an issue with the edge_clk_latency_ data structure. So create a small design with two clocks and show this